Real-time Simulation Environment for Embryonic Networks

Abstract

Throughout the time, evolution processes of biological organisms are characterized by self-healing, adaptation and not the last, surviving abilities. Mimicking all these features in VLSI circuits, this has lead to technological improvements that make possible the designing and building of fault-tolerant systems. Because complexity is almost a requirement of these systems, in order to exhibit the above mentioned features, designing and simulating them efficiently, require a tailored modeling and simulation environment. By studying the design and implementation flow of embryonic systems, it can be concluded that a modeling and simulation environment has to have the capabilities of modeling through a programming language, as close as possible to the implementation methods, and in the same time the power of simulating in real-time. The paper focuses on presenting a new modeling and simulation environment, giving an example of a structure for an embryonic system. [PUBLICATION ABSTRACT]

Headnote

Abstract - Throughout the time, evolution processes of biological organisms are characterized by self-healing, adaptation and not the last, surviving abilities. Mimicking all these features in VLSI circuits, this has lead to technological improvements that make possible the designing and building of fault-tolerant systems. Because complexity is almost a requirement of these systems, in order to exhibit the above mentioned features, designing and simulating them efficiently, require a tailored modeling and simulation environment. By studying the design and implementation flow of embryonic systems, it can be concluded that a modeling and simulation environment has to have the capabilities of modeling through a programming language, as close as possible to the implementation methods, and in the same time the power of simulating in real-time. The paper focuses on presenting a new modeling and simulation environment, giving an example of a structure for an embryonic system.

Keywords: Real-time; Simulation environment; Embryonic system; Fault-tolerant system; Bio-inspired

I. INTRODUCTION

All the living organisms are endowed by nature with distinct evolution capabilities like self-healing abilities, surviving and adaptation, encoding them genetically. To design complex fault-tolerant hardware, these capabilities are a key feature to include [1, 2]. Most of the computer aided design and simulation environments, typically involved in these processes, either natural or replicated in hardware, approach them in a classical fashion, where the simulation runs for a while and after done, the results are presented for analysis or further post processing. The design and build time of a bioinspired hardware system is drastically reduced if the simulation runs in real-time, presenting to the user how a process evolves and where or when the process fails [3]. In such a system, a bug in software code is very difficult if not impossible to spot or trace when using a non real-time simulation. In a classical simulation, although the results present various design defects, the complexity of the system hinders the defect tracing.

A major advantage of a real-time simulation is that it can accept external stimuli or even altering parts of the simulated model, during run time [3]. Such a feature is beneficial either for design improvements or debugging. From different points of view, the simulation of embryonic systems raise several types of difficulties. One is regarding the incapability of most present software tools available on the market to simulate multiple digital structures with complex VLSI processors, organized in network architectures. Although there are some tools capable of simulating networks in real-time, their internal models are described through electronic schematics, which make them difficult to develop compared to a coding approach. Beside of this problem, also those simulation environments, which are suited for digital circuits synthesizing, usually compute (through numerical integration algorithms) only analogical magnitudes like currents and voltages, and such processes increase significantly the simulation time, excluding them from the real-time category. For this reason, new research instruments and advanced study tools are far welcome for engineers involved in complex digital systems simulation and development.

The tradeoffbetween different combination of features constrains the user somehow when he or she must take a decision when choosing the best suited simulation environment.

It is true that fault-tolerant hardware systems include parts that can't be simulated in real-time or simply has no relevance for this type of simulation, but practice shows that in most cases these parts can have a simplified model or even excluded from the real-time simulation. The real-time modeling and simulation environment, named DigChipSim, presented in this paper is aimed to overcome some of the above mentioned shortcomings. Also, it is given an example of how a fault-tolerant system is simulated using the DigChipSim environment.

II. THE DIGCHIPSIM ENVIRONMENT

The most common units of a simulation environment are the design, simulation and post processing. The DigChipSim environment presents a versatility in design, characterized by allowing the user to describe the models in a programming language, easing their development, use custom GUIs or even write external simulators in their preferred design environment [4].

The structure of the simulation environment of DigChipSim, written in Turbo Delphi [5], presented in Fig. 1, shows the three mentioned units: design, simulation and post processing. The Design unit from Fig.1 includes the environment's design application, named Digital Chip Simulator, used for schematic design and model coding and two design applications or environments which are not actually parts of the DigChipSim environment, but are required for advanced use. These last two design environments are 3rd party environments, used for writing custom GUIs and custom simulators. The thick arrows from Fig. 1 show the design application or environment [5, 6] that is used for the different simulators of the DigChipSim environment.

In the real-time simulation unit, there are included a design simulator, which is the main simulator, several user simulators and a custom GUI simulator [6]. The input/output interface from the design simulator is limited because complex GUI interfaces or simulators built by the user are always more suited for the simulated design than any other solution. The simulator that loads custom user GUIs is called FlashWin and loads GUIs in a swf (Shockwave Flash) format [7].

The last unit, called post processing, comprise several applications that process the simulation results, data that is not needed to be processed in real-time during simulation.

The main idea of the simulated application, given as an example, is based on an artificial organism with a general structure like in Fig. 2.

An artificial organism, like that presented in Fig. 2, is comprised from a large number of artificial cells, organized as active cells and spare cells [8]. For the presented example, the application uses only a cluster of cells, made by a 3x3 matrix and several external devices, resulting in an embryonic machine. The structure of this embryonic machine is presented in Fig. 3.

For the design/modeling step of the process, the main window of the Digital Chip Simulator application from the DigChipSim environment is presented in Fig. 4.

Fig. 4 shows the main window of Digital Chip Simulator in which there can be seen a design board, a toolbar at the right hand and the program's window menu. The first stage of a design in DigChipSim is capturing the circuit, which will be simulated later. For simplicity, a circuit designed in DigChipSim, consists only of integrated circuits, no matter their complexity and connection wires between them. The integrated circuits used in a design will be called further chips or blocks. To have a fully customizable design, the user is able to model the blocks by writing Pascal code for each block. After finishing circuit capture and blocks' modeling, the user hits the "build" button to make the design available for simulation.

Using the chip editor presented in figure 5, there can be designed chips at a maximum size of 400 pins (100 pins on each side). Based on a list of variables, took from the chip model, the user assigns each pin to a variable, either in a manual fashion or using the AutoArrange feature. The algorithm behind this feature takes the list of variables which will be assigned to pins, and based on their direction (either input or output) the input variables are assigned to the pins from leftand top sides and the output variables are assigned to right and bottom sides of the chip. Thus, the chip is sized on x and y dimensions accordingly.

Using the chip editor, there can be also loaded pictures that will be overlayed on the chips on the design board. This feature helps the user to easily understand the role of each chip in a big schematic. The overlayed images are automatically sized to the owning chip.

In the same editing window, the user assigns a chip model for the chip being edited [10].

The chip editor allows also simple transformations of the chip, like clockwise / counter-clockwise rotations, horizontal and vertical rotations and X / Y sizing.

Editing the chip models is done using the Chip Models and Code Editor window from the Digital Chip Simulator application, presented in Fig. 6.

Comparing to most of the real-time modeling and simulation software available on the market, one of the strengths of DigChipSim environment is that it allows the user to describe the models using programming code [11]. The models are organized in a tree fashion, with the top-level models being assigned to chips on the design board and the other models working as subprograms/subcircuits.

Every model may have code for initialization, for loop and for finalization. The code describing a subcircuit can be called as a subprogram from its upperlevel parent model. The loop code from the top-level models is executed in a sequential fashion, directly controlled by the simulator.

A feature required by the simulation of an embryonic system is that the environment should allow for assigning multiple chips to the same model, for example, giving to all the artificial cells from the Fig. 2, the same code. Each chip model has its own code and variables which are dynamically created for each assigned chip. The variables of input and output type must be assigned to the chip's pins in order to be used as communication lines. Variables that are of internal type can't be assigned to the chip's pins and are used for internal purposes only.

Another advanced feature is the execution rate of each model when there is needed to simulate various parts of the model at different speed. For example, in the artificial cells used, there are subcircuits that have to run at full speed and a core processor which runs slower. This translates in a physical counterpart that behaves like a combinatorial logic from a shiftregister, for example, and a sequential logic from a virtual processor.

Different other useful features of the chip model and code editor include previewing the overlay images of assigned chips, saving / loading a chip model to / from file, adding comments to variables and calling the chip editor to automatically generate the chip based on the variables' list.

III. REAL-TIME SIMULATION UNITS

The simulation principle of the presented simulator consists of a data transfer method that synchronizes data at chip transfer level by grouping simulation tasks in two main categories: chip models execution and connection execution. This approach requires that all inputs of the simulated models remain constant during models' execution and all outputs remain constant during connections' execution. Thus, no matter the complexity of a model in regard to other model, the execution time of each model lasts exactly one iteration, which means a simulation step.

The execution of a model consists of computing all its state equations by taking a set of inputs and updating its outputs accordingly. The graphical updates and communication with other simulators are also done here. Executing the connections (that link the models) means updating models' inputs with outputs from other models. Fig. 7 shows a flowchart of the simulation principle presented in this paper.

In contrast with other simulators, this one does not mix the models' and the connections' executions thus making it capable of modeling digital circuits of a wide range of complexities. By executing the models on multiple processors and synchronizing their results after execution, there can be achieved a high simulation performance.

This simulator can also be used in analog models that do not require simulation of currents but only voltages, however, the support for analog simulations is limited. The main disadvantage of this simulation principle is that it can't be used for models where the precise timing is a critical factor. For those types of simulations, the best suited are the non real-time ones.

For the reason of being able to let the user interract in a friendly manner with the simulation, the DigChipSim environment provides the FlashWin simulator, which is capable of loading user defined GUIs, designed in a 3rd party environment. For example, a user defined graphical interface that can be loaded in FlashWin is a .swf (ShockWave Flash) file which is based on named objects. In this way, the user can design an application specific GUI that is the closest model to its real counterpart as shown in Fig. 8.

This interface accepts simulation stimuli from the user either by using the mouse or using the keyboard. The simulation interface loaded in FlashWin, presented in Fig. 8, lets the user "kill" the artificial cells with a mouse click. The feedback to the user becomes complete by graphically updating the state of the simulated models. For example, the control wires glow if their state is active; the artificial cells show the active genes.

Another advantage of this approach is the easiness in debugging because the user can see in real-time, how every part of the simulated model works. The FlashWin simulator can be run on a different computer because it can be connected to the main simulator of DigChipSim through a TCP/IP link [12]. For local connections, FlashWin can use a COM (Component Object Model) interface [13], which is more accessible than TCP/IP.

For the embryonic machine presented further in this paper, a custom user defined simulator was used, given in Fig. 9. This is a standalone program like those presented above, which is designed to simulate a switched reluctance machine in real-time for low velocities [14]. This kind of simulator can be tailored even more than the user defined GUI loaded in FlashWin, because it is built from scratch in a programming environment. The user defined simulator communicates with the main simulator of DigChipSim through a TCP/IP connection, making it able to run on a different computer [15].

IV. A FAULT-TOLERANT EMBRYONIC SYSTEM SIMULATED IN DIGCHIPSIM

The artificial cells, briefly presented in Fig. 2 and Fig. 3, are used as motor controllers for a 4-phased, 8/6 switched reluctance machine. From the block diagram given in Fig. 8, loaded as a user defined GUI in FlashWin, it can be seen that there is a 3x3 matrix of artificial cells, constituting a cluster, an external device, used as interface to a personal computer, a multiplexer, named σ, for control buses, a power inverter and a motor. The cell from the top-right corner, having the matrix notation Cell_1_3, is assigned as the active cell to drive the motor. Its control algorithm, also called artificial gene is highlighted with letter "B". Other active cells highlight other genes, for their own control algorithms. The total number of genes available in a cluster is given by the number of active cells, which is 5. The other 4 artificial cells are used as spare cells and each of these spare cells can replace any other cell by simply activating the appropriate gene.

Fig. 10 presents a simulation result in which the cell 1_3, used to drive the motor, is faulted at some point and it is replaced by spare the cell 2_3. [8]

The replacing process consists of detecting the fault by monitoring the control bus of the active cell by the spare cell and activating the appropriate gene to continue the control. Later, also the spare cell 2_3 is faulted and it becomes replaced by the spare cell 3_2. Although Fig. 10 does not present any other cell faults inside the cluster, they can be handled further because there are still two remaining spare cells. The red arrows from Fig. 10 show which cell is actively driving the control bus for the motor phases at a different stage of the simulation.

Another important information given by Fig. 10 is represented by the motor phases waveforms, which show that in case of a cell fault, the spare cell generates as quick as possible the control signals to keep the motor running. In any case, it can be observed that the embryonic array, represented by the artificial cells, keeps its immunity during this process, showing active the same genotype (A, B, C, D, and E).

Most of the modeling and simulation details of the presented example, are given in figures Fig. 3 to Fig. 9, took as snapshots after the modeling stage. There are shown details from electronic schematics to model's architecture and even simulation flow.

In the schematic from Fig. 8, the "Power Inverter" is a component that appears in a physical application but can be omitted in a simplified model, where the motor phases can be controlled directly with logic signals, e.g.: ON/OFF. Because the simulated switched reluctance motor (Fig. 9) can be controlled with such signals, the "Power Inverter" may have no model. In the presented model, the phase currents are not used because the motor is controlled only from its rotor's position. This feedback must go to the artificial cell that is responsible for controlling the motor (according to its active gene) and all the spare cells. In case of a fault in the artificial cell network, there are spare cells ready to replace the faulted cell and continue the controlling process by being connected both to the electrical machine and the sensors.

V. CONCLUSIONS

The paper is focused on presenting a real-time modeling and simulation environment specially tailored for embryonic systems, named DigChipSim. This environment can be used for modeling by designing electronic schematics that contain models described in a programming language. The simulation is done in a real-time fashion and allows also processing of the results.

The presented theoretical approaches and real-time simulation software toolkit could be a useful support for computer-aided modeling and simulation of complex bio-inspired hardware systems or sophisticated embryonic processes. Implementing basic properties of living organisms like self-healing or surviving in hardware architectures, highly reliable embryonic systems become possible to be developed.

ACKNOWLEDGMENTS

This paper was supported by the project "Doctoral studies in engineering sciences for developing the knowledge based society-SIDOC" contract no. POSDRU/88/1.5/S/60078, project co-funded from European Social Fund through Sectorial Operational Program Human Resources 2007-2013.

References

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