Epitaxial lift-off process for gallium arsenide substrate reuse and flexible electronics

Abstract

Epitaxial lift-off process enables the separation of III-V device layers from gallium arsenide substrates and has been extensively explored to avoid the high cost of III-V devices by reusing the substrates. Conventional epitaxial lift-off processes require several post-processing steps to restore the substrate to an epi-ready condition. Here we present an epitaxial lift-off scheme that minimizes the amount of post-etching residues and keeps the surface smooth, leading to direct reuse of the gallium arsenide substrate. The successful direct substrate reuse is confirmed by the performance comparison of solar cells grown on the original and the reused substrates. Following the features of our epitaxial lift-off process, a high-throughput technique called surface tension-assisted epitaxial lift-off was developed. In addition to showing full wafer gallium arsenide thin film transfer onto both rigid and flexible substrates, we also demonstrate devices, including light-emitting diode and metal-oxide-semiconductor capacitor, first built on thin active layers and then transferred to secondary substrates.

ARTICLE

Received 16 Oct 2012 | Accepted 7 Feb 2013 | Published 12 Mar 2013

Epitaxial lift-off process enables the separation of IIIV device layers from gallium arsenide substrates and has been extensively explored to avoid the high cost of IIIV devices by reusing the substrates. Conventional epitaxial lift-off processes require several post-processing steps to restore the substrate to an epi-ready condition. Here we present an epitaxial lift-off scheme that minimizes the amount of post-etching residues and keeps the surface smooth, leading to direct reuse of the gallium arsenide substrate. The successful direct substrate reuse is conrmed by the performance comparison of solar cells grown on the original and the reused substrates. Following the features of our epitaxial lift-off process, a high-throughput technique called surface tension-assisted epitaxial lift-off was developed. In addition to showing full wafer gallium arsenide thin lm transfer onto both rigid and exible substrates, we also demonstrate devices, including light-emitting diode and metal-oxide-semiconductor capacitor, rst built on thin active layers and then transferred to secondary substrates.

DOI: 10.1038/ncomms2583

Epitaxial lift-off process for gallium arsenide substrate reuse and exible electronics

Cheng-Wei Cheng1, Kuen-Ting Shiu1, Ning Li1, Shu-Jen Han1, Leathen Shi1 & Devendra K. Sadana1

1 IBM T. J. Watson Research Center, 1101 Kitchawan Road, Yorktown Heights, New York 10598, USA. Correspondence and requests for materials should be addressed to C.-W.C. (email: mailto:[email protected]

Web End [email protected] ).

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Gallium arsenide (GaAs), with its high electron mobility and direct bandgap, has been employed in high performance RF electronics and optoelectronics for

decades14. On the basis of thermodynamics calculation, its bandgap lies at the energy for the theoretical maximum efciency of single junction (SJ) solar cells and makes it an ideal material for high efciency solar cells5. However, the high cost of GaAs substrates hinders them from being widely adopted in certain applications, in particular for solar cell because of a need for large amounts of the material. A typical thickness of a GaAs substrate is around a few hundred micrometres, and only a few micrometres or nanometres thickness is required to fully absorb the solar energy or serve as the active layer for device operation. Therefore, the material cost can be potentially reduced if thin device layers can be separated from the substrate while keeping the substrate intact and ready for another epitaxial growth.

In 1978, Konagai et al.6 proposed a method which is known today as epitaxial lift-off (ELO) to separate a device layer from a GaAs substrate by using hydrouoric acid (HF) to selectively etch a AlGaAs (aluminium compound) sacricial layer inserted between the device lm and the substrate (Fig. 1(a)). Subsequently, this same method has been applied by many researchers to successfully peel GaAs thin lms from the parent substrates and transfer them onto desirable substrates for various applications7,8. The major drawback of this method arises from the high surface roughness of the parent substrate as well as reaction residues left on the substrate after the ELO process, and post-process steps, for example, chemical-mechanical-polish or chemical etching, typically required to reclaim the substrate9. In addition, HF is a lethal and highly corrosive acid requiring special handling and extra protection. Compared with typical short processing times with HF in silicon industry, the conventional ELO process takes hours to complete, which potentially increases the exposure risk for operators and the operating cost. Hence, developing a new ELO process with different chemistry that enables the direct reuse of the substrate is very desirable to lower the overall cost. Although HCl-based etchant was proposed and used by several researchers to selectively etch AlGaAs10,11 or other sacricial layers1214, the possibility of reusing the substrate directly with these methods has not been explored. In this paper, we demonstrate a new ELO process where aluminium-arsenide based sacricial layer and HF-based etchant are replaced with phosphide-based materials and HCl. This new approach minimizes the amount of post-etching residues and provides the surface passivation that keeps the surface smooth during ELO process, leading to direct reuse of GaAs substrate.

ResultsMechanism of the ELO Process for reuse of GaAs substrates. A viable ELO process for manufacturing should satisfy three essential conditions: (1) the surface of the reused substrate needs to be residue-free, and have low surface roughness (the root-mean-square (RMS) roughness of an epi-ready GaAs wafer is about 0.3 nm); (2) the properties of subsequent layers grown on reused substrates should be identical to that of the rst released lm; (3) the throughput of the ELO process should be high to drive down overall cost. Fig. 1(b) illustrates the chemical reactions of the conventional ELO process and atomic-force microscopy (AFM) image of the post-ELO substrate surface. The attack of the substrate by the HF and the residues formed during the sacricial layer etching result in the increase of RMS roughness from 0.3 to 14 nms range. Chemical reactions

between AlAs and HF have been well studied10,15,16 and the two major reactions are shown below:

AlAss 3HFaq ! AlF3s AsH3g 1

AlAss 3HFaq 6H2O ! AsH3g AlFnH2O6 n 3 n s

3 nF aq nH2O

2

Three primary byproducts from these etching reactions are AlF3, [AlFn(H2O)6 n] (3 n) and AsH3. AsH3 is gaseous and can form bubbles and diffuse away from the interface to the atmosphere. AlF3 and [AlFn(H2O)6 n] (3 n) , on the other hand, are solid and hard to dissolve into the solution. Besides these primary byproducts, solid As2O3 can also be generated on the substrate depending on the oxygen concentration of the etchant17. Table 1 summarizes the solubility of the solid byproducts from the conventional ELO process18. Although AlF3 and As2O3 do not have extremely low aqueous solubilities, it is evident that they still remain on the substrate surface after ELO and cause a high surface roughness, which can be seen in Fig. 1(b). Moreover, HF used in this process slowly attacks GaAs and induces additional surface roughness. Post-chemical etching with thermal cleaning can potentially reduce the surface roughness to the level of the original wafer. However, the remaining contaminants still seriously degrade the quality of regrown lms and device performances9. To completely remove all these contaminants and achieve high quality regrown lms, multi-step chemical polishing with different sacricial (protection) layers was recently proposed, with the penalties of the higher cost for extra epitaxial growths and HF still being used as the main etchant19.

The abovementioned issues in the conventional ELO process can be mitigated by employing a different sacricial layer that can be selectively etched by a non-HF solution, while leaving no insoluble etching byproducts on the GaAs surface. One advantage of compound semiconductors is that their physical and chemical properties can be manipulated by alloying different group III and V elements. For example, phosphide-based materials (InGaP, InAlP, InP and so on) have been widely applied as etch stop layers for the selective etching of arsenide based materials (GaAs, InGaAs and so on), and vice versa. It is well known that hydrochloric acid (HCl) can etch phosphide-based materials14,2022 and the reaction is shown in Equation (3):

InXPs HClaq ! lnCl3aq XCl3aq PH3gX Al; Ga

3

The gaseous PH3 diffuses away from the interface and the rest of the etching byproducts are highly soluble (their solubilities are shown in Table 1); thus, no residues are left on the wafer surface. Fig. 1(c) illustrates the new ELO process and AFM image of the post-ELO surface. The wafer surface is atomically at with RMS roughness of merely 0.349 nmsignicantly improved over conventional ELO (Supplementary Fig. S1). This improvement comes from the almost innite etch-selectivity between GaAs and phosphide with the HCl etchant. In order to verify that HCl attacks GaAs much less compared with HF, we soaked blanket GaAs wafers in HCl or HF for 24 h and the AFM images afterwards are shown in Fig. 2(a). RMS roughness of the 24h-HCl wafer is only 0.327 nm, much lower than the 1.666 nm RMS roughness after 24 h in HF. This result indicates that HF attacks GaAs severely and causes excess surface roughness even without the ELO process. This can be explained through

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a

Etchant

Device film

GaAs substrate

Device film

Sacrificial layer

GaAs substrate

HF 49%

RMS 2.955 0.214 nm

15 nm

b

Conventional ELO

HF

Device film

AlAs

GaAs substrate

AsH3

AIF3

AlF(H2O)

0.2 0.4 0.6 0.8 m

0.2 0.4 0.6 0.8 m

c

Novel ELO

HCI 36%

RMS 0.349 0.031 nm

HCI

15 nm

Device film

InAlP

GaAs substrate

PH3

InCl3

AICI3

Figure 1 | Concept of epitaxial lift-off (ELO) process and post-ELO GaAs surface morphologies with conventional and novel ELO processes.(a) Schematic illustration of general ELO process. (b,c) Schematic illustrations of the chemical reactions near the sacricial layer/etchant interfaces during the conventional and the novel ELO process and the three-dimensional AFM images of the GaAs surfaces after the processes. Here, indium aluminium phosphide (InAlP) was taken as an example of the sacricial layer of the novel ELO process.

Table 1 | Solubility of etching products from conventional and novel ELO process.

Solubility of etching productsConventional ELO Novel ELOCompound mole per 100 g H2O g per 100 g H2O Compound mole per 100 g H2O g per 100 g H2O

AlF3 6.71 10 3 0.5 InCl3 0.88 195.1

Al(OH)3 1.28 10 6 9.47 10 5 AlCl3 0.52 45.1

As2O3 1.04 10 2 2.06 GaCl3 Very soluble

As2O5 2.97 10 14 4.6 10 12

* NaCl as a reference for solubility - NaCl 0.615 36.0

Abbreviation: ELO, epitaxial lift-off.

NaCl is taken as the reference of solubility18.

possible etching mechanisms for GaAs with HF and HCl, as shown in Equation (4). In contrast to the etching of GaAs by HF that is thermodynamically favourable (DG o0), the reaction with HCl is suppressed (DG 40)18.

GaAss 3HXaq ! GaX3aq AsH3g X F; Cl 4DGHF 112:2kJ/mole;

DGHCl 75:5kJ/mole

Therefore, the etch rate of GaAs in HCl is much lower and the surface remains smoother. Note that in the particular alloy example in Equation (3), aluminium is not required for selective

etching, but it can accelerate etching of the sacricial layer. Moreover, because only undissociated HCl molecules interact with phosphide, the throughput is greatly enhanced by using concentrated HCl with the new ELO process20,23,24. The use of HCl as an etchant also poses signicantly lower risks compared with highly lethal and corrosive HF. These attributes makes the new ELO process much safer and economical for manufacturing compared with the conventional method.

In addition to reducing substrate etching to minimize surface roughness, surface passivation of GaAs by acids also has an important role. Fig. 2(a) shows that GaAs wafers soaked in diluted acids display higher RMS roughness than those soaked in concentrated acids. It is well known that the combination of

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a

15 nm

Hydrofluoric acid (HF)

Hydrochloric acid (HCI)

HF 49%

RMS 1.666 0.119 nm

HF 5%

RMS 2.756 0.098 nm

HCI 36%

RMS 0.327 0.12 nm

HCI 5%

RMS 0.626 0.052 nm

0 nm

Concentrated acid

Diluted acid

b c

Passivate

O O O

O

F H

Passivate

CI H

Etch

Ga

Ga

AS As

Figure 2 | Surface morphologies of GaAs surfaces during ELO process. (a) AFM images of the GaAs substrate surface dipped in both concentrated and diluted HF and HCl for 1 day. (b,c) are the schematic illustrations of the surface chemistry of GaAs dipped in HF and HCl, respectively.

acid or base with oxidants can be an effective GaAs etchant and dissolved oxygen can serve as an oxidant. On the other hand, both HF and HCl can passivate the surface and prevent it from being oxidized by dissolved oxygen (Supplementary Fig. S2 and Supplementary Methods). The competition between surface passivation by acids and etching by dissolved oxygen determines the surface roughness at different acid concentrations. These processes are illustrated in Fig. 2(b,c). It has been proven that the GaAs surface becomes highly hydrophobic (like H-terminated surface that forms by dipping Si into HF) after it is dipped into HF or HCl25,26. The surface gallium atoms are passivated by uorine or chlorine atoms and the surface arsenic atoms are possibly passivated by hydrogen atoms25,2729. Higher acid concentrations provide better coverage of passivated atoms and leave fewer unprotected sites to be oxidized by dissolved oxygen. The main difference between HCl and HF is that HCl only passivates the surface while HF not only passivates the surface, but slowly etches the bulk GaAs. In order to verify the hypotheses discussed above, a GaAs sample was placed into diluted (5%) HCl purged with pure N2 to release dissolved oxygen from the solution for 2 days(Supplementary Fig. S3 and Supplementary Methods). The nal surface roughness is 0.358 nm and is almost identical to the GaAs sample soaked in concentrated HCl for 1 day, suggesting that dissolved oxygen in diluted HCl roughens the surface. To quantify the etch rates of GaAs with HCl and HF, GaAs samples were left in 36% HCl, 5% HF and 49% HF for 9 days. The etch depths were measured to be 3, 12 and 100 nm, respectively, (Supplementary Fig. S4 and Supplementary Methods). We attribute the minor etching of 36% HCl to dissolved oxygen in HCl and conrm the signicantly higher GaAs etch rate in HF.

Demonstration of substrate reuse. As a smooth surface does not guarantee re-usability of the wafer after ELO9, SJ solar cell structures were grown and fabricated on both the original substrate and the reused substrate to conrm the quality of the regrown layers. Figure 3(a) shows current density versus voltage (JV) characteristics measured under AM1.5 sun condition, and

Fig. 3(b) shows the external quantum efciencies (EQE) of both cells. No substantial difference in short circuit current (Jsc), open

circuit voltage (Voc), ll factor (FF), efciency (Z) and EQE was observed. We attribute some slight mismatches of solar cell performance to fabrication process variations. The fact that no performance degradation is observed on the cell fabricated on the reused substrate demonstrates the feasibility of direct reuse of GaAs substrates by applying phosphide base sacricial layer and the use of concentrated HCl as the etchant.

Surface tension-assisted ELO process as a new lift-off method. Finally, one major throughput bottleneck in conventional ELO processes is the slow lateral etch rate of the sacricial layer. Generally speaking, the lateral etch rate of the sacricial layer is determined by two consecutive processes: the diffusion of the etchant from the solution to the etching front and the reaction of etchant with the sacricial layer. The etch rate is initially limited by the chemical reaction until the diffusion distance of the etchant causes the etch rate to be limited by the diffusion rate. Performing the ELO process in the chemical reaction rate limited regime is preferred as it can maximize the overall etch rate. In order to do so, several methods with sophisticated setups, for example, weight-assisted ELO30 and etching assisted by roller15,31, were developed to accelerate the ELO process. However, these are only single-wafer solutions with consequent low throughput.

To enhance our ELO process throughput, we developed a new method called surface tension-assisted (STA) ELO and its concept is shown in Fig. 4(a). The wafer coated with the photoresist is placed obliquely with an angle (y) of 120 from the solution surface, and HCl is added to the level of the etching front. The wafer surface is protected by the photoresist from being attacked by the acid. As discussed above, the GaAs surface becomes hydrophobic in HCl, so the lm oats on the surface of the HCl solution after lift-off. During the STA-ELO process, surface tension pulls the lm away from the substrate and attens the lm on the surface. In the meantime, HCl replenishes the space between the lifted-off lm and the substrate via the capillary

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a b

J (A cm2 )

25 20 15 10

5 0

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

E.Q.E.

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

400

Reused sub.

New sub.

Jsc = 17.7 (mA cm

2)

Jsc =18.2 (mA cm

2)

Voc =1.019 V

FF = 0.73[afii9834] = 13.0% [afii9834] = 13.5%

FF = 0.75

Voc =1.009 V

500

600

700

800

900

V (V)

Wavelength (nm)

Figure 3 | Performance of single junction GaAs solar cells fabricated on new and reused substrates. (a) Current density versus voltage (JV) characteristics of GaAs SJ solar cells grown and fabricated on new (green symbols) and reused (blue symbols) substrates. Inset: solar cell performance parameters. (b) EQE of solar cells grown on new (green) and reused (blue) substrates as a function of wavelength. No anti-reection coating (ARC) was applied.

<100>

Surface tension

HCI

a

b

[010]

REtching

[001]

[afii9835]

[011]

c

Figure 4 | Surface tension-assisted ELO process. (a) Schematic illustration of the surface tension-assisted (STA) ELO process. (b) Etching rate of InAlP in HCl as the function of crystallographic direction. The maximum etching rate locates at o1004. All the data were normalized by maximum etching rate. (c)

Recorded images of the lifted-off lm during STA-ELO process. The minor image distortion was caused by the vibration of hood. The InAlP sacricial layer thickness is 100 nm.The temperature of HCl solution was kept at 60 C and the process took about 8 h. The average lateral etching rate is B5.9 mm h 1 in this demonstration. The etching rate could be increased by further optimization of the process, structure and setup.

force, which causes the process to continue to be reaction limited. Figure 4(b) shows the relationship between the normalized etch rate of the phosphide sacricial layer and the crystallographic direction of the wafers. The study reveals a fourfold symmetry where the maximum etch rate occurs along the o1004 axis, as the etching fronts are terminated by {111} A faces32. As a result, the wafer needs to be tilted along the o1004 axis for the highest etch rate and to keep the etching front along the o1004 direction. This allows the surface tension of the solution to apply a uniform force on the lifted-off lm. The complete STA-ELO process is shown in Fig. 4(c) and in the Supplementary Video S1. The camera reection on the lifted-off lm demonstrates how the surface tension of the solution results in a at surface. The lifted-off lm can be transferred onto almost any substrate for various applications, including either a rigid (Fig. 5(a)) or a exible substrate (Fig. 5(b)). After the ELO process, the parent wafer only

needs to be rinsed thoroughly and then cleaned with a standard wafer cleaning procedure before the next epitaxial growth.

DiscussionAfter the STA-ELO process, the GaAs thin lm can be transferred onto any thermal-expansion-coefcient (TCE) matched substrates (for example, soda-lime glass) without using any metal supporting layer during ELO process. This helps keep the GaAs surface pristine and the newly transferred lm compatible with epitaxy systems for subsequent epitaxial growth. Another advantage is that devices can be fabricated on the GaAs surface rst before the lm containing the devices is released from the parent substrate. By these means, the device yield can be largely improved, as it reduces the constraint on the highest process temperature allowable imposed by the thermal mismatch between

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the lm and the carrier substrate. Figure 6 demonstrates some conceptual devices fully fabricated in advance before our STAELO process: (a) a light-emitting diode (LED) transferred onto Si

substrate (Supplementary Fig. S5), and (b) metal-oxide-semiconductor capacitors (MOSCAP) transferred onto exible tape. Red light emission in Fig. 6(a) suggests that the integrity of the LED was preserved after the lm transfer. Figure 6(b) shows capacitancevoltage measurements from GaAs MOSCAPs at different frequencies, demonstrating no observable difference between devices measured before and after the thin lm transfer.

In conclusion, the direct reuse of GaAs substrates has been demonstrated by a newly developed ELO process. Residue-free and atomically at post-ELO surfaces, resulting from the use of phosphide base sacricial layers and HCl-based etchants, results in high quality regrown GaAs thin lms and enables the regrowth of solar cell structures without observable performance degradation. Furthermore, STA-ELO, a high-throughput lift-off technique, is developed and employed to transfer GaAs thin lms onto both rigid and exible substrates. This technique opens up a suite of potential applications using IIIV materials.

Methods

Material growth. IIIV growth, including both arsenide and phosphide base materials, was performed in Thomas Swan close coupled showerhead cold-wall MOCVD system. High-purity N2 was employed as the carrier gas, and the substrate temperature and the reactor pressure were kept at 650 C and 100 Torr during the growth. Epilayers were grown on either 200 n-type (Si doped) or p-type (Zn doped) epi-ready GaAs wafers depending on the device structures. Trimethylgallium (TMG), Trimethylaluminum (TMA) and Trimethylindium (TMI) were used as element III precursors. Arsine (AsH3) and Phosphine (PH3) were used as element V sources for growing arsenide (V/III 23) and phosphide (V/

III 400) materials, respectively. DiSilane (Si2H6) provided n-type dopants and

dimethylzinc was used for p-type doping.

Experiment, device fabrication and characterization. The layers of IIIV solar cells were grown on a 200 N-type GaAs wafers. The wafers were then cut into two pieces with one piece serving as a reference. The other piece went through ELO process to separate the solar cell structure from the substrate, and it was then reloaded into MOCVD system and the same layer structure was regrown. After the regrowth, these two pieces were processed in parallel to complete the nal solar cell

a

b

Figure 5 | GaAs thin lms transferred to rigid and exible substrates. (a) Demonstrations of the transferred GaAs thin lms to the rigid Substrate (left, GaAs on 400 Si wafer. Center, GaAs on curved solid object. Right, GaAs on glass) and (b) exible substrates (left, GaAs on tape. Right, GaAs on exible sheet). The thickness of the GaAs ranges between 13 mm and the diameter of the GaAs is 200 except the lm transferred to the curved solid object.

Before After

5045403530252.0 1.5 1.0

VG (V) VG (V)

5045403530252.0 1.5 1.0

A = 7.85 105 (cm2)

Nd = 11018 (cm

3)

1,000 kHz

500 kHz 100 kHz

50 kHz 10 kHz

Capacitance (pE)

tAl203 =10 (nm)

Figure 6 | Demonstration of transferred devices via novel ELO process. (a) Transferred 200 AlGaAs LED on 200 Si wafer and the optical image of light emission. Scale bar, 5 cm. (b) CapacitanceVoltage (CV) characteristics of n-GaAs MOSCAP before and after being transferred to a exible tape. Inset: the optical image of MOSCAPs on a mother substrate and on a exible tape. Scale bar, 1 cm.

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structures, which is shown in Supplementary Fig. S6. A detailed process ow is described below.

1 1 cm2 mesa was dened by photolithography and etched to the bottom

contact layer by NH4OH/H2O2/H2O. The bottom n-ohmic contact was made with thermal evaporated AuGe/Ni/Au and a lift-off process, followed by rapid-thermal annealing (RTA) at 450 C for 1 min in N2 ambient. Then, a shadow mask was applied to dene the top p-ohmic contact region by depositing Au/Ni and 1 mm thick Ag to lower the series resistance. After removing the shadow mask, the top contact layer (p-GaAs) was selectively etched by citric acid/H2O2. No RTA was performed for p-type ohmic contact and no anti-reection coating was applied on the solar cells. The JV characteristics of GaAs SJ solar cells were measured under simulated AM1.5 solar spectrum at 1 sun intensity.

A similar process ow for the solar cell was applied for LED device fabrication, and the layer structure as well as the nal device structure of LED are shown in Supplementary Fig. S7.

MOSCAPs were fabricated by the following process ow. After surface degreasing and ammonia-base native oxide etching, the sample was transferred to an ALD reactor and 10 nm thick Al2O3 was deposited at a substrate temperature of 250 C, followed by 600 C post-deposition annealing for 15s. The substrate contact was dened by photolithography and Al2O3 was removed by buffered oxide etch (BOE) solution and n-ohmic contact was made by thermal evaporated AuGe/Ni/ Au and a lift-off process, followed by N2 RTA at 450 C for 1 min. Top Al electrodes of 100 mm in diameter were deposited by thermal evaporation through a shadow mask. Finally, the fabricated MOSCAPs were transferred onto a piece of exible tape. CV characteristics of MOSCAP were measured using Agilent 4284A precision LCR metre at frequencies from 1 MHz to 10 kHz. The layer structure and the nal MOSCAP structure are shown in Supplementary Fig. S8.

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Acknowledgements

The authors thank Dr Tze-Chiang Chen, Dr Ghavam Shahidi, Dr Harold Hovel, Dr Joel

P. de Souza, and Dr Hsin-yu Tsai for all the supports and professional discussions and

suggestions in this work in IBM Watson Research Centre. The authors also thank Dr

Yang Li, Dr Nan Yang, Adam Jandl, Kunal Mukherjee, Ryan Iutzi, Tim Milakovich and

Prithu Sharma for helps in IIIV materials growths at MIT.

Author contributions

C.-W.C. designed and executed the study and wrote the manuscript. K.-T.S. assisted

C.-W.C. to execute all the experiments. N.L. performed the AFM measurements. The

images were taken with assistance from N.L. S.-J.H. and L.S. contributed to the devel

opments of the thin lm transfer process. S.-J.H. made gures and contributed to the

manuscript preparation. D.K.S. supervised the project. All the authors joined the

discussion and provided comments.

Additional information

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How to cite this article: Cheng, C.-W. et al. Epitaxial lift-off process for gallium arsenide

substrate reuse and exible electronics. Nat. Commun. 4:1577 doi: 10.1038/ncomms2583

(2013).

NATURE COMMUNICATIONS | 4:1577 | DOI: 10.1038/ncomms2583 | http://www.nature.com/naturecommunications

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