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A floating body electrostatic discharge (ESD) protection circuit positioned between and coupled to an I/O pad and an internal circuit is presented. A small NMOS transistor is used to control the body of a main NMOS transistor. When the small NMOS transistor is triggered, the body of the main NMOS transistor remains grounded. If the small NMOS transistor has not been triggered, the body of the main NMOS transistor remains in a floating state, lowering the range of the snapback voltage. As a consequence the ESD protection circuit is able to function more rapidly. The proposed ESD protection circuit is designed in 65 nm CMOS technology.
Introduction: Electrostatic discharge has been considered as a major reliability threat in the semiconductor industry for decades. It was reported that electrostatic discharge (ESD) and electrical overstress (EOS) are responsible for up to 70% of failures in IC technology [1]. Therefore, each I/O must be designed with protection circuitry that creates a discharge path for the ESD current. As CMOS technology scales down, the design of ESD protection circuits becomes more challenging. This is due to thinner gate oxides and shallower junction depths in advanced technologies. A multi-finger gate grounded NMOS (GGNMOS) is the most widely used ESD protection circuit because of its active discharge mechanism and compatibility to CMOS technologies. Sometimes the multi-finger GGNMOS cannot be uniformly turned on during ESD stress. Only several fingers of the GGNMOS are turned on and this often causes a low ESD level. As a result, the conventional GGNMOS is vulnerable to robustness in transporting and carrying. The gate floating technique [2-4] is a useful method to reduce the trigger voltage. However, ESD protection circuits using these methods are not effective for high robustness.
In this Letter, an ESD protection circuit with the floating body technique using an NMOS transistor is proposed for low trigger voltage and high robustness. This work has been successfully verified in a foundry's TSMC 65 nm CMOS process.
Proposed ESD protection device: The gate floating technique is widely used to reduce trigger...