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A novel clock distribution scheme is proposed for high-speed DRAM to minimise clock-skew among data buffers. It has ideally zero-skew characteristic by employing folded clock lines and phase blending circuits. Simulation results show that the maximum clock-skew between two receivers located 4 mm apart is less than 20 ps, regardless of process, voltage, and temperature variations.
Introduction: Most high-speed DRAMs employ phase-locked loops (PLLs) or delay-locked loops (DLLs) to reduce clock-skew between system clocks and data from DRAMs. Nevertheless, owing to the different clock arrival time to each data buffer, it is difficult to sufficiently reduce the clock-skew among decentralised data buffers. To avoid this problem, the clock distribution scheme must be considered carefully. Unfortunately, conventional clock distribution schemes [1] widely used in microprocessors are not suitable for DRAMs, since it is difficult for most commercial DRAM fabrication technologies to assign some dedicated layers for clock distribution. Dynamic power consumption of the clock system is another critical issue in high-speed DRAM. The peak current driving large clock loads induces power supply noise, which often affects other sensitive circuits. In this Letter, we propose a novel clock distribution scheme for high-speed DRAMs. It has ideally zero-skew characteristic and significantly reduces dynamic power consumption by exploiting folded clock lines (FCLs) and low-voltage clock signals. In addition, the proposed scheme is robust to process, voltage, and temperature (PVT) variations.
Clock distribution: Fig. 1 shows the proposed clock distribution scheme. FCLs run across clock receivers 1-n, the clock-skew of which is minimised. They are terminated with matched resistors (RT) to prevent signal reflection. A clock signal is transmitted from the clock driver to the folding point (nFD), denoted as forward clock (FCK). After passing the folding point, it returns to the driver again, denoted as return clock (RCK). Note that the sum of electrical length of FCK and RCK from the clock driver is always the same at any arbitrary locations on the FCL, e.g. the sum of electrical length of FCK and...