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The twin SONOS memory (TSM) transistors for 2-bit/cell non -volatile-memory (NVM) application are presented and their reliability is evaluated so that they can be applied to next generation NVM technology. This new memory, which is implemented by the damascene gate and outer sidewall spacer processes, shows a high reliability down to 80 nm gate length.
Introduction: SONOS devices using trapped charges in a nitride layer have received much attention, since SONOS non-volatile-memory (NVM) devices are inherently free from drain to floating-gate coupling [1] and are able to show a 2-bit=cell storage scheme that utilises different physical locations to store programmed charge [2]. Though the multi-bit=cell scheme is definitely attractive in a SONOS memory device, it would be more difficult to achieve 2-bit characteristics in the sub-90 nm regime due to its critical issue of spatial charge redistribution and spreading after its program [3]. A physically separated storage node scheme using either an inner sidewall spacer [4] or outer nitride spacer [5] has been proposed to overcome these limiting factors. In terms of device manufacturability and gate controllability, however, both the inner sidewall scheme and the outer nitride spacer scheme are hard to scale down into nano-scale regime in spite of their small features. To improve manufacturability and gate controllability of a 2-bit=cell SONOS device, we have fabricated twin SONOS memory (TSM) transistors with total gate length of 80 nm using the combined process of the damascene gate and the outer sidewall spacer scheme that make physically separated storage nodes. Through this novel scheme, we have been able to obtain the experimental data which demonstrate highly reliable 2-bit=cell SONOS memory transistors beyond the next generation NVM technology.
Device fabrication: TSM transistor fabrication started with a p-type bulk silicon wafer. After cell transistor isolation, the deposition of bottom...