Test methods for crosstalk-induced delay and glitch faults in network-on-chip interconnects implementing asynchronous communication protocols

Headnote

Abstract: Variations in crosstalk is an added source of delay and glitch faults in System on Chips built with deep sub-micron technology, especially in chips using wide and long buses. Many of these faults, in such sub-micron chips, may only appear when the chip works at normal operating speed. These crosstalk-induced faults are more serious in systems built with Globally Asynchronous Locally Synchronous principles. The authors propose efficient methods for at-speed testing of such faults in asynchronous links connecting, for example, two switches/routers of an network-on-chip communication infrastructure. The proposed delay test method has the property that all faulty chips are identified but some good chips may also be characterised as faulty with a small probability. The authors give an analytical analysis regarding this probability as a function of probability of delay fault and number of applied test instances. A simple and pure digital BIST hardware is also proposed, which is represented at Register Transfer level to implement the delay test method. A method is also proposed for detecting glitches on control lines in a handshaking-based communication link; thereafter it is shown how the method can be extended for detecting glitch faults on data lines. The proposed test methods for detecting delays and glitches provide a complete scheme for detection of crosstalk-induced faults in links in an on-chip communication infrastructure using asynchronous handshaking communication protocols.

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1 Introduction

For deep sub-micron (DSM) chips, testing for defects causing breaks and short circuits is not enough. To ensure a high quality in the delivered chips, defects that cause too long delay or too much crosstalk need to be tested as well. This is especially important in relatively long wires connecting different parts like IP cores of a System-on- Chip (S°C) [1], Newer chip technologies have smaller wires and transistors and run at higher speed than before. Wires are also very closely packed. Effects of parasitic capacitances and inductances [2-4] need to be considered during design of a chip and testing is needed on the manufactured chips to check if these parasitic effects go beyond the tolerance limits and affect the function of the chip.

The chip designer needs to ensure that the expected crosstalk does not cause the chip to fail....