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Translation from original language as provided by author
As the national digital television industry policy is issued, the middle and high-end video post-processing chips are welcomed by the market. The video post-processing chip design is very complex, including many algorithms, such as noise reduction, frame rate conversion, scaler and de-interlacing. As ASIC design needs lots of manpower and financial resources which bring in high risk, this paper designs an FPGA based general purpose video post-processing platform for video post-processing IP design and the subjective validation of different kinds of algorithms. The research of this paper can be summarized as follows: Firstly, the video post-processing hardware platform design is introduced. This platform is composed of Xilinx XUPV5LX110T board and video decode daughter card. According to the principle of high speed circuit PCB design, a professional analog video decode daughter card with several kinds of analog video input interfaces and a professional digital video decode card with two channels of HDMI input interfaces are designed. Secondly, the existing de-interlacing algorithms are reviewed and their performances are specifically analyzed in details. Based on the drawbacks of these algorithms, an improved edge directed de-interlacing algorithm is proposed. Experimental results show that the proposed algorithm performs well on interpolating image details, especially the low angle edge and passes the tests in Silicon Optix HQV benchmark. Thirdly, the validation IP of the video post-processing system is designed. This IP consists of I2C interface configuration, video decode, video format conversion, de-interlacing, video encode and display. Experiments results show that this video post-processing platform has high level stability and meets the real-time