Charge carrier mobility in thin films of organic semiconductors by the gated van der Pauw method

Abstract

Thin film transistors based on high-mobility organic semiconductors are prone to contact problems that complicate the interpretation of their electrical characteristics and the extraction of important material parameters such as the charge carrier mobility. Here we report on the gated van der Pauw method for the simple and accurate determination of the electrical characteristics of thin semiconducting films, independently from contact effects. We test our method on thin films of seven high-mobility organic semiconductors of both polarities: device fabrication is fully compatible with common transistor process flows and device measurements deliver consistent and precise values for the charge carrier mobility and threshold voltage in the high-charge carrier density regime that is representative of transistor operation. The gated van der Pauw method is broadly applicable to thin films of semiconductors and enables a simple and clean parameter extraction independent from contact effects.

ARTICLE

Received 21 Nov 2016 | Accepted 14 Feb 2017 | Published 11 Apr 2017

Thin lm transistors based on high-mobility organic semiconductors are prone to contact problems that complicate the interpretation of their electrical characteristics and the extraction of important material parameters such as the charge carrier mobility. Here we report on the gated van der Pauw method for the simple and accurate determination of the electrical characteristics of thin semiconducting lms, independently from contact effects. We test our method on thin lms of seven high-mobility organic semiconductors of both polarities: device fabrication is fully compatible with common transistor process ows and device measurements deliver consistent and precise values for the charge carrier mobility and threshold voltage in the high-charge carrier density regime that is representative of transistor operation. The gated van der Pauw method is broadly applicable to thin lms of semiconductors and enables a simple and clean parameter extraction independent from contact effects.

DOI: 10.1038/ncomms14975 OPEN

Charge carrier mobility in thin lms of organic semiconductors by the gated van der Pauw method

Cedric Rolin1, Enpu Kang1, Jeong-Hwan Lee1, Gustaaf Borghs2, Paul Heremans1,3 & Jan Genoe1,3

1 IMEC, Large Area Electronics, Kapeldreef 75, Leuven B-3001, Belgium. 2 KU Leuven, Department of Physics and Astronomy, Celestijnenlaan 200d, Leuven B-3001, Belgium. 3 KU Leuven, Department of Electrical Engineering, Kasteelpark Arenberg 10, Leuven B-3001, Belgium. Correspondence and requests for materials should be addressed to C.R. (email: mailto:[email protected]

Web End [email protected] ).

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The charge carrier mobility is a key performance criteria for organic semiconductors1. High-mobility values allow fast device operation as needed for low-cost electronics on

large areas with performance meeting market demands25. Mobility is conveniently extracted from thin lm transistors (TFT) characteristics using the standard gradual channel approximation model6,7. This approach evaluates the mobility of charges during their transport through the high-density accumulation layer at the semiconductor-dielectric interface8,9. This value is therefore directly representative of transistor operation and is a relevant parameter for device integration into circuits10,11.

In high-mobility organic semiconductors and in short channel devices, however, the relative importance of the contact resistance Rc can be such that the standard model is no longer appropriate for mobility extraction12,13. Proper parameter extraction is complicated by the fact that carrier injection from the contact into the semiconductor is often mediated by the gate voltage VG.

When this is not properly taken into account, it leads to serious over-estimation of the mobility1416. Therefore, a more accurate, yet simple, method is highly desirable for the proper evaluation of mtfsc, the charge carrier mobility in thin lms of organic semiconductors in the high-charge density accumulation layer. In this denition, mtfsc characterizes the contact-independent translational motion of charge carriers across the thin lm semiconductor material, over distances that may be larger than typical grain size. In this sense, mtfsc encompasses extrinsic barriers to transport such as grain boundaries and therefore does not necessarily correspond to the intrinsic intra-grain charge carrier mobility of the monocrystalline semiconductor17.

In this work, we proposed the gated van der Pauw (gVDP) method for the characterization of thin lms of several organic semiconductors. The van der Pauw (VDP) method is a geometry-independent four-contact electrical measurement widely used to evaluate the sheet conductance ss of thin continuous slabs of semiconductor materials18,19. The use of a gate to modulate charge density in VDP devices is, on the other hand, hardly documented in the literature2022. In this communication, we show that the gate in the gVDP structure creates transport conditions similar to TFT operation. We propose a simple model for the interpretation of gVDP characteristics, allowing for an extraction of mobility and threshold voltage VT. We then

fabricate devices based on thin lms of seven different organic semiconductors and show that their measurements are independent of Rc and are representative of the electrical

characteristics of the thin lm in the high-charge density regime. This validates the gVDP method as a simple and accurate technique to extract mtfsc.

ResultsThe gated van der Pauw method. A simple VDP device topology is presented in Fig. 1a. The thin conductive lm is patterned as a square and four contacts are applied to its corners. Although the lm shape can be arbitrary, semiconductor lms with four-fold symmetry simplify data analysis and increase accuracy. In the structure of Fig. 1a, the size of the contacts must be negligible relative to the size of the square, but this condition is relaxed when using clover-leaf shaped lms, which simplies alignment of the patterned layers. For electrical measurement, a current I1 is

sourced in contact 1 and drained at contact 2, which is grounded and used as a reference. The potentials V3 and V4 in isolated contacts 3 and 4 are measured. The potential distribution and current density streamlines in a square VDP device are obtained from a two-dimensional nite element analysis solving Maxwells equations with realistic ss 1.5 mS per square and I1 1 mA

(Fig. 1c). The current density is highest along the edge 12 and decreases towards side 34 as the current path lengthens. The dashed equipotential lines V3 and V4 delimit the probed region where the voltage is sensed, away from the source and drain contacts 1 and 2.

For ss extraction, we rst measure R12 V3 V4jjI1, the resistance

in the probed region alongside 12. The measurement of R21 along the same side is obtained by reversing the direction of the current while grounding contact 1. Next, the resistances along the three other sides of the square are measured in a similar way and the eight resistance values are averaged as

R. Finally,

thanks to the four-fold symmetry of the lm, the sheet conductance of the lm is simply obtained as ss ln 2 p R.

Strong points of the VDP method are the following. As in four point probe (FPP) measurements, the contacts that sense voltage are non-injecting, thereby limiting contact effects. Furthermore, contrarily to the FPP method, no geometrical dimension enters VDP data analysis: device imperfections and misalignments are averaged out by measuring all four sides in both directions.

A common gate is introduced by fabricating the VDP device on a highly doped silicon wafer covered with a thin layer of SiO2 as

gate dielectric. A gVDP device cross-section is shown in Fig. 1b, where all contacts are projected on the same plane for

a

c

V (V)

4

1.2

I1

1

2

1

0.8

VC

0.6

Electrodes

0.4

b

Semiconductor

0.2

Insulator

Common gate

3 0

Figure 1 | The gated van der Pauw method. (a) Top view of a van der Pauw device with square-shaped thin semiconductor lm. (b) Pseudo-cross-section view of a van der Pauw device fabricated on a common gate and insulator. All contacts are projected on the same plane for convenience. (c) Potential map and current density streamlines in the van der Pauw device in linear regime. The scale bar is 0.5 mm long. The simulation is parameterized with a current I1 1 mA owing through a lm with sheet conductance ss 1.5 mS sq 1. The dashed lines are equipotential lines V3,V4 and VC (V3 V4)/2.

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NATURE COMMUNICATIONS | DOI: 10.1038/ncomms14975 ARTICLE

a

30

25

I1 (A)

20

10

20.4

V 1(V)

V(V)

15

10

5

0

40 35 30 25 20 15 10 5 0 5 10

b

V1 VC

2

; 2 and after simplication:

ss mtfscCI VG VT VC

j j; 3 with VC V3 V42. In the parallel plate capacitor formed by the

gate/insulator/semiconductor stack, the charge density is d CI VG VT VC

j j, where VC approximates the potential in

the probed region of the gVDP device. Equation 3 is very similar to the gradual channel approximation model of a TFT in the linear regime that is derived from equation 1 with VS 0 and

g 0:

ss

ID VD

VG (V)

40 35 30 25 20 15 10 5 0 5 10 VG (V)

45 5

18

12

Lin.

Sat.

9

6

3

0.2

0.1

LW mappCI VG VT

VD

2 :

0.0

4

Here, VD2 approximates the potential in the TFT channel and mapp is the apparent mobility, which, in contrast to mtfsc, is affected by

the contact resistance.

Gated van der Pauw device operation. All devices fabricated in this study were based on the bottom gate-top contact staggered topology depicted in Fig. 1b. Substrates were 2 2 cm highly

doped Si wafers acting as common gate with B125 nm thermally grown SiO2 as insulator. After a surface treatment with self-assembled monolayers, we thermally evaporated thin (r30 nm)

lms of organic semiconductors through a shadowmask. Then we evaporated metallic electrodes using a second aligned shadowmask. For gVDP devices, we favored clover leaf patterns that allow easy-to-apply large contacts and are tolerant against misalignment. Also, TFT devices with various channel lengths were processed simultaneously. They were used to generate transmission line measurements (TLM) from which reference mapp and Rc were extracted.gVDP electrical characterization requires a current source to

control I1. The bias on contact 1, V1, is automatically adjusted to keep a constant current, while sweeping the gate voltage VG.

Furthermore, the gVDP device is best measured when the grounded electrode 2 is also the contact that sinks charge carriers, as shown in Fig. 1a. Therefore, for p-type (n-type) semiconductors, holes (electrons) are injected by the positively (negatively) biased contact 1, resulting in a positive (negative) current I1 owing from 1 to 2. In the case of p-type organic semiconductor C10-DNTT (2,9-didecyl-dinaphtho-[2,3-b:20, 30;-f]-thieno-[3,2-b]-thiophene) with gold contacts, Fig. 2a shows the evolution of V1 as a function of VG for a broad series of I1.

We distinguish two operating regimes from the shape of the V1 curves. At high (positive) VG, V1 has a linear dependence with VG with a slope equal to unity. At low (negative) VG, |V1| is small and slowly decreases as |VG| increases. These regimes are respectively called saturation and linear regimes, as they correspond to the eponymous regimes observed in TFT operation.

The two regimes are also apparent in Fig. 2b, where V1,

VC V3 V42 and V4V3 are detailed for I1 2 mA. In the

saturation regime, VC follows V1 very closely, while V4V3 takes

c

6

5

1 )

4

I1

15 I1 = 2 A

[afii9846] s ( S sq

3

2

1

0

Figure 2 | Characterization of a gVDP device. (a) Potential V1 of the injecting contact 1 as a function of gate voltage VG for different currents I1. (b) Evolution with VG of three characteristic potentials V1,VC (V3 V4)/2

and V4V3. Data measured with I1 2 mA. (c) Sheet conductance ss of the

semiconductor lm extracted using the gVDP method at different I1. ss is

plotted as a function of VGVC. The error bars are computed by averaging over 8 measurements, 2 along each side of the gVDP structure. The line is linear t. Inset: photograph of the gVDP device based on a thin lm of C10-

DNTT shaped as a clover-leaf. Scale bar is 0.5 mm long.

convenience. Applying a potential VG to the gate relative to the grounded contact 2 leads to the accumulation of charges at the semiconductor/insulator interface. This results in an increase of ss that promotes current ow. The relationship between ss and VG is explained by a model derived from the TFT generic charge drift model given by:23

ID LW ss VD VS

mtfscCI

VG VT VS

g2 VG VT VD

g2 g 2

;

1

where ID is the TFT drain current, L and W are the channel length and width, VS and VD are the potential at the source and

drain contacts, CI is the gate insulator capacitance per unit area and g is the mobility enhancement factor. To model gVDP operation with equation 1, we simply treat the probed region in the VDP device as a TFT with source and drain at potentials V4 and V3 respectively, and with geometrical dimensions

L/W ln(2)/p, as demonstrated by van der Pauw for a square

VDP structure18. Assuming that mtfsc is unaffected by potential variation, that is g 0, the generic TFT model is rewritten as:

I1 ln 2

p ss V3 V4

j j

mtfscCI

2 VG VT V4

2 VG VT V3

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a

7

a

105

6

104

5

1 )

R CW(k cm)

4

103

Metal contact AgAu MoOx/Au

[afii9846] s ( S sq

3

Device:

102

2

1

101

0

100

45 40 35 30 25 20 15 10 5 0

VGVC or VGVD/2 (V)

100

VG (V)

VGVC (V)

b

7

0

b

3.5

6

1

3.0

2

5

2.5

2 V1 s1 )

3

1 )

V T(V)

[afii9846] s ( S sq

4

2.0

4

3

1.5

[afii9839] app (cm

5

2

1.0

6

1

7

0.5

8

0.0

0 0 125 150 175 200

25

50

75

45 40 35 30 25 20 15 10 5 0

L (m)

Figure 3 | Comparison with TFT characteristics. (a) Sheet conductance ss of the semiconductor thin lm measured from a gVDP device and three TFTs with different channel lengths taken from a TLM device. Lines are linear ts delivering the apparent mobility mapp and the threshold voltage VT of the TFTs.

Inset: photograph of the TLM structure with a thin C10-DNTT lm and Au top contacts. Scale bar is 0.5 mm. (b) Evolution of mapp and VT with TFT channel

length. mapp, VT and the error bars are obtained from the linear regression on the ss versus VGVD/2 characteristic of each TFT, as shown for three values of

L in (a). The line is a t to the mapp data. The dashed and dotted horizontal lines respectively represent the mtfsc and VT from the corresponding gVDP device.

60 55 45

50 40 35 30 25 20 15

Figure 4 | Effect of contact resistance on gVDP measurements.(a) VG dependence of contact resistance Rc extracted from TLM measurements. The error bars are obtained from the linear regression over the total resistance versus channel length data that yields Rc. The TLM devices are based on C8-BTBT lms with three different top contact materials yielding large differences in Rc. (b) ss is extracted by gVDP from the same C8-BTBT lms with different contacts, at currents I1 ranging from0.04 to 5 mA. The overlap of the ss versus VGVC plots show the independence of the gVDP method from Rc. The error bars are computed by averaging over 8 measurements, 2 along each side of the gVDP structure. Lines are linear ts. Inset: photograph of a sample with side-by-side TLM and gVDP devices. Scale bar is 1 mm long.

a small constant value of 0.19 V. In saturation, the majority of the semiconductor lm is subjected to a limited potential drop. Its average potential VC is close to V1. In this almost equipotential region, V1 (hence VC) automatically adjusts to a value substantially higher than VG so that the charge density dsat CI VG VT VC

j j remains constant at a value allowing

current ow. In contrast, the vicinity of grounded contact 2 is depleted of charge carriers. A potential drop through the semiconductor lm, from BVC to V2 0 V, creates a lateral

eld sufcient to maintain current through this depletion zone. In the linear regime, Fig. 2b shows that VC is exactly the half of the small V1. In this case, as represented in the simulation of Fig. 1c, the potential linearly drops when current ows from contact 1 to 2. The transition between regimes is most visible in the V4V3 curve in Fig. 2b. It takes place at VGBVT corresponding to the closure of the depletion zone around contact 2. Further VG decrease into the linear region yields an increase in charge carrier density so that dlin4dsat cst. The increase of dlin is

compensated by the progressive lowering of the lateral electric eld (seen in the decrease of V1 and V4V3). This maintains a constant current I1 throughout the linear regime.

We repeated the measurement detailed in Fig. 2b on both directions of all four sides of the C10-DNTT gVDP device shown in the inset of Fig. 2c. After averaging the eight measurements, the sheet conductance of the semiconductor lm ss is extracted using the VDP method for various VG and I1. Following equation 3, ss is plotted as a function of VGVC in Fig. 2c. With this choice of

the X-axis, all characteristics fall along the same straight line. In contrast, Supplementary Fig. 1 shows the ss versus VG plot that does not lead to any useful interpretation. The line in Fig. 2c is a linear t using equation 3. Its slope and intercept with the X-axis give mtfsc 6.50.1 cm2 V 1 s 1 and VT 6.50.2 V,

respectively. The straightness of the curve in Fig. 2c conrms that mtfsc has negligible eld dependence (g 0). Also the small error

bars in Fig. 2c, and the limited s.d. in the extracted data show that the gVDP approach effectively reduces error and increases precision. Finally, the two regimes observed earlier, do not appear in the evolution of ss with VGVC. Indeed, ss is extracted from the probed region between equipotentials V3 and V4 drawn in Fig. 1a. Since this region remains far from the depletion zone in the vicinity of grounded contact 2, it always experiences a linear current transport, even when the gVDP device is driven in saturation. In consequence, the extraction of ss is independent of the regime of operation and data can be collected across a broad VG range.

Comparison with TFT measurements. In parallel to the gVDP device discussed so far, we prepared a TLM device with ten TFTs based on the same C10-DNTT lm. The TFTs had a channel width W 630 mm and channel lengths L ranging from 28 to

194 mm (Supplementary Fig. 2 shows some TFT transfer and

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Table 1 | Electrical characteristics of thin evaporated C8-BTBT lms with three different contact materials.

Contact material

Rc (kX cm) TLMVG 60 V

ltfsc (cm2 V 1s 1) gVDP

VT (V)

TFT Sat VD 60 V

lapp

(cm2 V 1s 1) TFT SatVD 60 V

lapp

(cm2 V 1s 1) TFT LinVD 1 V

VT (V)

TFT Lin VD 1 V

VT (V) gVDP

MoOx/Au 6.670.29 4.11.6 2.60.5 10 1 3.90.1 16.95.9 14.92.5 12.60.7

Au 14532 3.61.2 4.61.4 10 2 4.00.1 37.24.1 43.05.2 15.10.3

Ag 34401200 4.50.8 4.56.0 10 4 3.80.1 42.41.3 29.06.9 13.20.4

All devices, TLM, TFT (W/L 630/28 mm) and gVDP are fabricated on the same sample.

0

output characteristics). Following equation 4, values of ss from three TFTs with different L are plotted in Fig. 3a as a function of VG-VD/2, along with the ss obtained from the gVDP device. The

TFT curves in Fig. 3a show a slight hysteresis with the back and forth sweep of VG, especially for the short channel devices. gVDP devices usually display the same level of hysteresis as long channel TFTs. In the case of the C10DNTT gVDP device discussed so far, this hysteresis is negligible.

The lines in Fig. 3a are linear ts using equation 4 that deliver the apparent mobility mapp and threshold voltage VT of the TFTs.

We used this approach to extract mapp and VT of all 10 TFTs in

the TLM structure. These are reported in Fig. 3b as a function of L. As L increases, the TFT sheet conductance curve in Fig. 3a shifts towards the gVDP curve. This progression also appears in Fig. 3b, where mapp tends towards mtfsc with the increase of L. This can be formalized using the following relation between mapp and

mtfsc24,25:

mapp

mtfsc

1 L1=2L

VGVC (V)

7

6

5

1 )

45 40 35 30 25 20 15 10 5 0 5

4

[afii9846] s ( S sq

3

2

1

45 40 35 30 25 20 15 10 5 0 5

VGVC (V)

Figure 5 | gVDP characteristics of thin lms of seven different organic semiconductors. VGVC dependence of the sheet conductance ss measured by gVDP on evaporated lms of six p-type semiconductors and one n-type semiconductor (NDI-cy6, upper X scale). I1 ranges from 0.04 to 10 mA. The lines are linear ts for data extraction.

; 5

where L1/2 is the channel length at which the contact resistance Rc is equal to the channel resistance Rch. Fitting equation 5 to mapp in Fig. 3b delivers mtfsc 6.80.4 cm2 V 1 s 1 and

a L1/2 201 mm. This value of mtfsc is within range of the

gVDP value (dashed line in Fig. 3b). The non-negligible L1/2 shows that Rc affects all TFTs in the TLM structure, which explains the performance degradation with the shrinking of L. In contrast, L variation does not affect the threshold voltage VT except for some scattering at low L caused by non-linearities in the ss curves (Fig. 3b). On average, the VT extracted from TFT measurements stays close to the value measured by gVDP (dotted line in Fig. 3b).

We now apply the standard TLM analysis. The variation of the total device resistance Rtot with L can be expressed as:13,24,25

RtotW RcW

L

mtfscCI VG VT

j j

: 6

This procedure yields mtfsc from the slope of the t and RcW

from its intercept with the Y-axis. Supplementary Figure 3 shows the tting procedure and the variation of the extracted parameters with VG. At VG 40 V, we obtain

mtfsc6.80.2 cm2 V 1 s 1 and RcW 33030 O cm. This

mtfsc exactly matches the value obtained from the tting of mapp in Fig. 3b. It is also within the error of the mtfsc measured in the gVDP device. RcW has a low value for organic TFTs that is characteristic of this material set14,25. TFT characteristics are nevertheless still seriously impacted by Rc because of the high-mobility, hence low Rch, of the C10-DNTT lm14. The gVDP device, on the other hand, shows an ideal behaviour and its characteristic in Fig. 3a represents the optimum towards which TFTs tend as the effect of Rc abates.

Inuence of contact resistance. The gVDP device studied so far has large dimensions. The electrical current path length is 41 mm, that is much longer than L1/2. This points to the fact that Rc in this device is negligible compared to its total resistance Rtot. Indeed, at VG 40 V, Rtot V1/I1B400 kO and we

estimate RcB4 kO from the dimensions of the contact pads. Our C10-DNTT gVDP device is hardly sensitive to contact effects and we cannot draw conclusions regarding the impact of more serious Rc on gVDP device operation. To examine this question, we fabricated gVDP and TLM devices based on evaporated thin lms of C8-BTBT (2,7-dioctyl-[1]benzothieno-[3,2-b][1]benzothiophene) that is more prone to contact problems. Indeed, C8-BTBT has a deep HOMO level of 5.8 eV

that complicates band alignment at the metal/semiconductor interface and poor vertical transport properties that complicate access to the channel in the staggered device topology26,27. Intercalating a thin layer of MoOx has been previously shown to improve injection28. In consequence, the three different electrode materials tested here, MoOx/Au, Au and Ag, yield a signicant variation in Rc, as can be seen from the TLM analysis in Fig. 4a.

Supplementary Figure 4 shows the TFT transfer characteristics measured in linear and saturation regimes of the shortest channel devices (W/L 630/28 mm). The TFT with the least resistive

contacts, MoOx/Au, is already affected by Rc as its ID and

ID

p

curves show substantial sublinear behaviour. Using worse contact materials completely depresses current in the linear regime and delays threshold in the saturation regime. Table 1 reports values of mapp and VT of these short channel TFTs extracted using the

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Table 2 | Electrical characteristics of thin evaporated lms of 7 different organic materials.

Organic semiconductor

Rc (kX cm) TLM

lapp,sat

(cm2 V 1s 1) TFT Sat

lapp,lin

(cm2 V 1s 1) TFT Lin

ltfsc

(cm2 V 1s 1) gVDP

VT (V) TFT Sat

VT (V) TFT Lin

VT (V) gVDP

C10-DNBDT 0.850.06 7.31.7 5.60.6 7.20.1 3.50.5 3.21.7 5.90.2

C10-DNTT 0.330.03 7.50.3 6.10.3 6.50.1 7.00.4 6.41.0 6.50.1

C8-BTBT 6.670.29 3.90.4 1.40.5 3.90.1 22.10.9 20.41.2 12.60.7

DPh-DNTT 0.920.06 3.70.3 3.30.4 3.30.1 6.00.6 7.91.9 8.90.7

DNTT 1.350.20 1.40.2 1.20.2 1.20.1 3.61.0 2.31.4 3.60.5

NDI-cy6 28.83.8 1.10.2 0.440.10 1.40.1 13.31.0 10.21.0 8.00.2 Pentacene 13.80.5 0.590.31 0.370.06 0.560.05 11.21.8 11.73.0 12.90.2

All devices, TLM, TFT (W/L 630/194 mm) and gVDP are fabricated on the same sample. R is given at the highest measured |V |. At least three TFTs per sample are measured in saturation and linear

regimes.

0.00

gradual channel approximation. The data show important spread reecting the low-quality of the transfer curves. In particular, VT is strongly affected by contact quality, especially in short channel devices. This is caused by a voltage offset set by the non-ideal contact between the reference injecting electrode and the transistor channel that is not taken into account in the gradual channel approximation model used for VT extraction29,30

Next, we measured gVDP devices fabricated on the same three samples with I1 ranging from 0.04 to 5 mA.We estimate from the

RcW value at VG 60 V that the worst contact material, Ag,

yields an estimate RcB40 MO in the C8-BTBT gVDP device. Such Rc is far superior to the expected lm resistance in the on region and dominates gVDP device operation. In spite of this, the ss characteristics of the three gVDP devices with different contact materials are linear and superimpose in Fig. 4b. The values of mtfsc reported in Table 1 have little spread and are all within error of each other. The values of VT, also in Table 1, show a slight spread that may have the same origin as the heavy VT spread seen above in TFTs, but of a much lower magnitude since the reference electrode is not the injecting one. The independence of mtfsc from

the nature of the contact material and the low spread in VT demonstrates that the gVDP method is quite insensitive to Rc, even when charge injection completely dominates transport as in the case of Ag contacts on C8-BTBT. In gVDP devices, the region probed by sensing contacts 3 and 4 is not inuenced by current injection and extraction in contact 1 and 2, respectively.

Other semiconductors. Besides C10-DNTT and C8-BTBT, we have investigated thin lms of ve other evaporated organic semiconductors, namely p-type C10-DNBDT (3,11-didecyl-dinaphtho-[2,3-d:20,30-d0]-benzo-[1,2-b:4,5-b0]-dithiophene), DPh-DNTT (2,9-diphenyl-dinaphtho-[2,3-b:20,30;-f]-thieno-[3,2-b]-thiophene), DNTT (dinaphtho-[2,3-b:20,30;-f]-thieno-[3,2-b]-thiophene), pentacene and n-type NDI-cy6 (2,7-Dicyclohexylbenzo [lmn] [3,8] phenanthroline 1,3,6,8(2H,7H)tetraone), also known as

DCyNTDA. Thin (B30 nm) lms of these materials were deposited in vacuum using growth conditions optimized for electrical performance. Characterization by X-ray diffraction and atomic force microscopy is given for all lms in Supplementary Fig. 5 and Supplementary Table 1. As discussed in Supplementary Note 1, this characterization shows that all thin lms are polycrystalline with growth patterns that are benecial to lateral charge transport: the lms are composed of a mosaic of two-dimensional grains with diameters ranging from 0.5 to 45 mm, that is much smaller than lateral gVDP device dimensions. These grains present a layer-by-layer microstructure with molecules standing on their long axis, which maximizes electronic coupling between adjacent molecular cores within the plane of the layer. In most cases, this continuous two-dimensional lm is covered by a dense matrix of tall-elongated

needles. This three-dimensional growth is symptomatic of a StranskiKrastanov roughening transition.

For all semiconductors, gVDP measurements deliver well-behaved ss characteristics (see Fig. 5) with a linear behaviour

a

VGVC (V)

40 35 30 25 20 15 10 5 0

1.50

1.25

1.00

1 )

[afii9846] s (S sq

0.75

[afii9846] s (S sq

0.50

0.25

1.50

b

1.25

1.00

1 )

0.75

0.50

0.25

0.00

tfsc

40 35 30 25 20 15 10 5 0 VGVC (V)

Figure 6 | gVDP devices based on organic lms patterned by scratching. The samples consist of thin (B30 nm) DNTT lms evaporated on common gate Si/SiO2 substrates, without patterning. Au contacts are then patterned by evaporation through a shadowmask. No mask alignment is necessary. Upon electrical characterization, a probe needle is used to manually pattern the DNTT lm by scratching it. (a) Scratched clover-leaf pattern. (b) Scratched square pattern. In both gures, the error bars are computed by averaging over 8 measurements, 2 along each side of the gVDP structure. The insets show photographs of the scratched devices. Scale bars are 1 mm long. Both devices were produced more than three months apart, which may explain the difference in VT.

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Table 3 | Fabrication conditions of electrical devices based on thin lms of different organic semiconductors.

Organic semiconductor

Material supplier Thermal gradient purication

Self-assembled monolayer

Deposition rate ( s 1)

Substrate temperature (C)

Contact material

C10-DNBDT Pi-Crystal Inc. 0 ODTS 0.20 135 Au

C10-DNTT Nippon Kayaku Co. 0 ODTS 0.10 80 Au

C8-BTBT Nippon Kayaku Co. 1 PETS 0.15 25 MoOx/Au*

DPh-DNTT Nippon Kayaku Co. 0 ODTS 0.15 70 Au

DNTT Nippon Kayaku Co. 1 ODTS 0.50 75 MoOx/Au

NDI-cy6 Lumtec Co. 1 TDPA 0.30 90 Ca/Ag

Pentacene Sigma-Aldrich Co. 1 ODTS 0.25 65 Au

*Au and Ag were also used to form lower quality contacts on C -BTBT.

conrming the eld-independence of the mobility. Data extraction using equation 3 is straightforward and mtfsc and

VT are reported for each material in Table 2. These values are compared with TFTs (W/L 630/194 mm) measured on the same

sample and analysed using the gradual channel approximation model. Even with long channel lengths, many TFT transfer curves show non-linearity that induce serious variations of mapp and

VT with VG and yield large s.d. over the TFT data in Table 2. The mobility of TFTs in the linear regime remains inferior to the thin lm mobility obtained by gVDP, mapp,linrmtfsc. This

difference increases as the importance of Rc relative to Rtot increases. On the other hand, in cases where Rc is not too high, the TFT mobility in the saturation regime mapp,sat is slightly

superior to mtfsc. The VT from TFTs and gVDP are similar for

most cases, except for material systems such as C8-BTBT with MoOx/Au, where an important interfacial energy barrier imposes a potential drop to charge the channel, resulting in an increase of the apparent |VT| of the TFT. In conclusion, contact non-idealities complicate TFT data analysis: non-linearity of the transfer characteristics compromises the quality of the extracted values, which depend on channel length and measurement regime. Such problems are absent in the gVDP method: Characteristics are linear, independent from device dimensions and measurement regime. They deliver trustworthy data with low-spread. In consequence, the gVDP method is an excellent probe to systematically relate electrical performance with the morphology and microstructure of thin lms of organic semiconductors. Such systematic growth studies are left to further work.

DiscussionOur motivation to develop the gVDP method is a simple and accurate extraction of the mobility of thin semiconductor lms that is representative of TFT operation. Other methods for contact-independent mobility extraction in the high-charge density regime exist such as Hall-effect measurements3133 and eld-induced time-resolved microwave conductivity1,34. These techniques, however, involve specialized measurement setups that are not broadly accessible. Other approaches exist to get mtfsc from

electrical measurements only. In the Results section, we have employed two methods to obtain mtfsc from TLM data. Although

accurate, TLM requires multiple device measurements and mobility extraction is weakened by the choice of VT that parameterizes equation 6 (refs 25,29,35). Methods involving advanced device modelling of TFT characteristics also exist, although they require setting up complex measurements and/or data treatment schemes3538.

Besides, mtfsc can be readily obtained from the measurement of a gated Four Point-Probe (gFPP) device, where the functions of current injection and voltage measurement are separated in the

channel39,40. The gFPP device fabrication is however complicated by the precise alignment of the voltage probes along the very edge of the semiconductor channel. This requires advanced patterning techniques and small variations in device geometry can compromise results41. In contrast, the gVDP device is much simpler to fabricate: using a clover-leaf pattern greatly simplies alignment down to small device size. Patterning of the organic layer is not even necessary: from a continuous DNTT lm with patterned Au contacts, we could roughly shape square and clover-leaf patterns with contacts at the corners by a simple scratching with a probe needle and still obtain excellent gVDP measurements (Fig. 6). Measuring the gVDP device is of the same complexity as the gFPP device measurement: Both require ve contacts. The data obtained are, however, more precise than in gFPP thanks to the averaging over all sides and the independence from geometric dimensions.

All lms analysed in this study were polycrystalline with random grain orientation and grain size much smaller than device dimensions. In consequence, they all displayed isotropic transport properties as evidenced by equal resistances R12 and R23 measured along two perpendicular edges of gVDP devices with four-fold symmetry. The gVDP method could, however, be extended to the treatment of anisotropic thin lm of semiconductors such as thin organic single crystals by adapting methods previously developed for the interpretation of VDP measurements carried out on anisotropic lms42,43.

Besides the small molecular organic semiconductors studied here, the gVDP method is generally suited to characterize a wide range of materials, such as semiconducting polymers, metal oxides, 2D materials and so on. The characterization of very low-mobility semiconductors is ultimately limited by the resolution of the measurement setup. Strategies to enhance current such as device downscaling and the use of stronger dielectrics can help these measurements. In the case of semiconductor/dielectric systems that display signicant eld-dependence of the mobility (g 4 0), a superlinear behaviour of the ss versus (VGVC) characteristic is expected. Data analysis would require the derivation of a model equivalent to equation 3 that still contains the mobility enhancement factor g.

In conclusion, we develop the gated van der Pauw (gVDP) method for the electrical characterization of thin semiconducting lms. This method combines the following advantages: (1) Device structure and fabrication constraints are the same as for thin lm transistors, allowing easy device integration and comparison.(2) Independence from contact effects that are detrimental to transistor characteristics. (3) Straightforward data analysis using equation 3 and precise parameter extraction thanks to the inherent averaging and independence from geometrical dimensions. We tested this method on thin lms of seven high-mobility organic semiconductors of both polarities, but it is applicable to any other thin lm semiconductor. We show that the

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gVDP method delivers accurate values for the charge carrier mobility and the threshold voltage of these lms in the high-charge density accumulation layer that is representative of transistor operation. Finally, this method is inherently independent from contact effects as the probed region is remote from metal electrodes. The gVDP device is therefore an excellent probe to systematically relate electrical characteristics to the morphology and microstructure of the thin lm semiconductor. It is also a great vehicle for physical studies that combine electrical measurements with other excitations, for example, magnetic eld or light.

Methods

Device fabrication. All devices were fabricated on SiO2/Si n substrates, the thickness of SiO2 was 125 nm. In the case of the NDI-cy6, an additional 100 nm of dielectric Al2O3 was grown by atomic layer deposition on top of the SiO2. All substrates were cleaned with solvents and exposed to ultraviolet-ozone for 150,

followed by a treatment with a self-assembled monolayer, as detailed in Table 3. Octadecyl-trichloro-silane (ODTS) and phenyl-ethyl-trichloro-silane (PETS) treatments were applied to the SiO2 surface by exposing the substrate to vapour of the liquid precursor at 140 C in a vacuum chamber for 1 h. n-Tetradecyl-phosphonic acid (TDPA) treatment was applied to the surface of Al2O3 by immersing the substrate in a solution of TDPA:2-propanol 5 10 3 M for 19 h. Thin

lms (B30 nm) of organic semiconductors were evaporated in high vacuum (1 10 8 torr) through a shadow mask, using optimized conditions given in

Table 3. This table also informs on the material suppliers and the thermal gradient purication used after receiving the material. Electrodes were vacuum deposited through a manually aligned shadow mask and with a substrate temperature of B 5 C. 5 nm of MoOx, 4060 nm of Au, 20 nm of Ca and 60 nm of Ag, were

deposited at rates of 0.05, 1, 1 and 2 s 1, respectively. The following procedure was used for the patterning of organic semiconductor lms by scratching shown in

Fig. 6: the sample was mounted and aligned on the probe station. A probe needle was put in contact with the sample, and the sample stage was moved to produce straight scratching lines parallel to edges of the Au patterns. Points of attention when shaping the gVDP device: (1) Contact size remains small in comparison with semiconductor pattern size: the radius of contacts in the square devices must be at least 10 times smaller than the square side length. The clover-leaf pattern provides much more relaxed size constraints. (2) Devices keep a four-fold symmetry. Thanks to the inherent averaging, the extracted value remains accurate, but the error increases in case of asymmetry.

Device characterization. All electrical measurements were performed either in air or in a N2 glovebox, using a probe station connected to an HP4156C parameter analyser. For gVDP device measurement, Contacts 1,2 and the gate were each connected to a source monitor unit, contacts 3 and 4 were each connectedto a voltage measurement unit. The parameter analyser was remote controlledby a Labview program that piloted both measurements along each side of the device. It is worth noting that a large potential difference between contact 1 (V1)

and the gate (VG) in the saturation regime can lead to bias stress effects resulting in a negative (positive) VT shift for p-type (n-type) semiconductors. This is avoided by setting a low voltage compliance on V1 (we used 40 V) and by avoiding too

large I1. The maximum I1 that can be sustained by a sample depends mainly on the semiconductor mobility, the gate capacitance and the length and width of the current path between contacts 1 and 2. For organic semiconductors, the typical range of I1 is between 10 nA and 10 mA. Throughout the measurements we always measured gate current IG to monitor gate leakage. In conventionalTFT analysis, the values of mapp were estimated by the conventional gradual channel approximation model given by equation 4 in the linear regime and mapp,sat

(2L/W)(1/CI)(@OID/@VG)2 in the saturation regime.

Data availability. The data that support the ndings of this study are available from the corresponding author on reasonable request.

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Acknowledgements

This work has received funding from the European Research Council under the European Unions Seventh Framework Programme (FP7/2007-2013)/ERC grant agreement no. 320680 (EPOS CRYSTALLI) and from the Research Foundation Flanders (FWO Vlaanderen) under the FWO-ARRS research collaboration program/grant number G0B5914N (ORSIC-HIMA). We thank Nippon Kayaku Co. for supplying the C8-BTBT, DNTT, C10-DNTT and DPh-DNTT used in this study.

Author contributions

C.R. and G.B. conceived the original idea. J.G. and C.R. derived the theoretical framework. E.K., J.-H.L. and C.R. fabricated devices. E.K. and C.R. performed the electrical characterization of the devices. J.G., G.B. and P.H. oversaw experiments. C.R. prepared the manuscript. All authors discussed the results and revised the manuscript.

Additional information

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How to cite this article: Rolin, C. et al. Charge carrier mobility in thin lms of organic semiconductors by the gated van der Pauw method. Nat. Commun. 8, 14975 doi: 10.1038/ncomms14975 (2017).

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