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In addition to standard system interfaces, most verification environments are likely to have customer specific or even proprietary requirements. Co-modelling is the ideal flexible, high-speed interface for quickly building these verification systems. Examples of general solutions include co-modelling products built on Vera, Co- Ware and the ARM instruction set simulator. For all solutions, Co- modelling provides a targetless high performance verification platform, a stable programming interface and an extendible modelling environment. The design of the application adapter and RTL transactor must be done prior to running co-verification. These models will vary in complexity and size depending on the design and type of the interface. Common applications such as data streaming are likely to yield adapters and trans-actors that can be built by modifying a standard template. With the initial release of TIP, IKOS delivers a simple data streaming co-modelling template. IKOS also plans to develop other co-modelling products for standard protocols like PCI and Ethernet, as well as a transaction compiler that can automate the generation of co-modelling interfaces.
A more detailed look of TAPI and the co-modelling macros depicts the interaction between the `C' functions on the host workstation and logic elements in the VStation. Figure 5 illustrates how co- modelling systems are architect by the user in `C' and Verilog. The logical data transfer between the `C' API and the co-modelling macros implement data transfer to and from the VStation. The RTL transactor manages the data transfer and interaction with the DUT. Once a communication channel has been opened with the TAPI_initInterface(_) function, the handle is passed to other TAPI functions to specify that channel. The input and output macros correspond directly to the TAPI_write () and TAPI_read() functions. Clocking in the DUT is controlled in the clock control co-modelling macro by gating the free running internally generate clock. In simple cycle-synchronous interfaces the clock control macro can be hooked directly to the data_done and new_data signals in the input and output macros so that each vector generates the clock. Alternatively, the user can create transactors that decode the data and generate arbitrary clock and data waveforms on the DUT. More advanced transactor design will utilize transaction density to achieve even higher performance.
The key to developing fast co-verification solutions is to find natural transaction boundaries between the platforms and use to the TIP interface to model those transactions. In determining optimal transaction boundaries, it is useful to understand the parameters that influence the performance of co-modelling solutions. A co- modelling solution consists of essentially three components, a system model or test bench connected to TAPI, an RTL transactor and the DUT. The verification speed is largely determined by four parameters, the amount of time spent per transaction in the system model, the maximum speed at which the DUT can run, the number of DUT cycles run per transaction, and the communication overhead between the work-station and hardware platform. Running more DUT cycles per transaction is usually the single best strategy to speed up co-modelling solutions. TIP performance is measured in transactions per second. More cycles per transactions multiplied by the same number of transactions per second gives more effective cycles per second. This is how a transaction based co-modelling interface can provide maxim performance. Optimising the system model or moving highly active parts of the system model into the emulator often results in performance wins. Since a co-verification solution can run no faster than its slowest part, IKOS has focused on creating the fastest workstation interface and transaction based co-modelling solutions.