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Abstract
As processors continue to exploit more instruction level parallelism, greater demands are placed on the performance of the memory systems. A novel modification of the processor pipeline called memory renaming is introduced. Memory renaming applies register access techniques to load and store instructions to speed the processing of memory traffic. The approach works by accurately predicting memory communication early in the pipeline and then re-mapping the communication to fast physical registers. Previous studies of data value and dependence speculation are extended. When memory renaming is added to the processor pipeline, renaming can be applied to 30%-50% of all memory references, translating to an overall improvement in execution time of up to 14% for current pipeline configurations.