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As DRAM prices continue to fall and most manufacturers experience financial hardships, only innovation and aggressive scaling will ensure a company's success. Because DRAM device scaling is applied mostly to DRAM cells, array architecture plays the most crucial role in determining chip size.
Traditionally, an 8F2 cell design and a folded bitline array have constituted mainstream DRAM architecture, proving to be the most reliable design in terms of manufacturability and DRAM array operations. Both symmetric array design and the dose physical location of bitline pairs help to achieve the most reliable senseand-restore operations for DRAM cells with folded bitline architectures.
Some DRAM manufacturers, notably Micron and Samsung, have also used a 6F2 cell design, providing about a 25 percent improvement in DRAM cell area. Although a 25 percent reduction in DRAM cell size is promising, some obstacles have arisen to adopting this technology for production. In addition to the process challenges naturally associated with smaller DRAM cells, such a design forces designers to use an open bitline architecture because of its tight pitch for bitline sense amplifiers. Open bitline architectures, however, are considered less immune to array noise.
In an open bitline architecture, each bitline pair comprises two bitlines located on either side of the bitline sense amplifier. In a folded bitline design, a bitline pair has two bitlines physically...