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Over the past decade, the semi-conductor industry has seen the evolution of myriad high-level languages for both design and verification. This proliferation has been compounded by the advent of a variety of point tools for each step of the ASIC design cycle. Last but not least, shrinking process geometries have enabled multimillion-gate systems-on-chip, adding another dimension of complexity to the development flow.
This combination of languages, tools, intellectual property and methodologies has morphed the traditional ASIC design cycle into a "hybrid model" process. With no readily available cookbook for selecting the best option for each stage of the cycle, many semiconductor companies have adopted the hybrid methodology to reduce risk and optimize time-to-market.
Verification consumes 60 to 70 percent of the total resources in a typical chip design cycle. The ASIC design flow requires verification at each level of abstraction, from architecture to silicon prototype. The challenge for engineers is verifying spec adherence for multiple abstractions. By its very nature, the verification process depends on language, methodology and SoC complexity in size, functionality and application.
Today, as more embedded software is being added to systems, software developers do not have access to the target hardware until there is a physical prototype. This leads to a need for common...