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As the argument rages on about whether high-gate-- count FPGAs can replace ASICs in certain applications, many in the industry have overlooked hybrid devices that offer designers the strengths of each. Although it is technically possible to design million-gate FPGAs, in reality these monolithic devices are not ideally suited for many high-complexity, high-performance applications.
At high gate counts, large FPGAs run into problems with time-to-market, performance and cost compared with ASICs with the same functionality. Additionally, monolithic devices do not take into account that designers of million-gate FPGAs are always using one or more intellectual-property (IP) cores in these devices, which means that a portion of the device contains either reusable cores or industry-standard functions. Hybrid devices combine core functionality in mask-- programmed silicon with the flexibility that programmable logic offers for custom features.
In an attempt to reap the advantages of both technologies, the field-programmable system chip (FPSC) blends system-level ASIC technology with programmable logic. The ASIC portion of the device is used for well-defined, industry-standard functions, while the programmable-logic portion makes it possible to incorporate user-defined functionality. This architecture provides the missing step in a migration path from FPGA to standard cell for higherperformance designs.
An IP core may be breadboarded on a midsize FPGA for prototyping, system verification and initial production, then ported to the FPSC for increased speed, functionality and cost reduction, and possibly later migrated to standard cell for mass production. FPSCs provide an important intermediary step that allows IP cores that, once verified, can be committed to mask-programmed...