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Version 3.1a will add a functional-coverage metric, extended VPI
Santa Clara, Calif. - The EDA market's largest suppliers have endorsed the Accellera standards organization's efforts to enhance the SystemVerilog hardware description and verification language, saying the changes will lead to better tools and better designs.
The enhancements, which will be based on feedback Accellera has received from vendors and users spotlighting some shortcomings in the current version 3.1 of the specification, will be implemented in SystemVerilog 3.1a, to be released to the IEEE next year. The two standards organizations have moved forward uneasily, and not in lockstep, to create a single standardized successor to Verilog. Representatives of Accellera outlined the enhancements to SystemVerilog 3.1 at the Accellera SystemVerilog Symposium here this month.
'Useful process'
"Accellera is focusing on making sure it addresses designers' needs," said Victor Berman, group director of language and intellectual-property standardization at Cadence Design Systems Inc. Noting that changes are a common part of language standardization, Berman said Cadence "sees the standardization effort as a useful process and will continue to support it."
"The planned, evolutionary enhancements will enable vendors to provide more comprehensive solutions, especially in the areas of verification and tool interoperability, with the new functional-coverage feature and enhanced VPI [Verilog Procedural Interface]," said Steve Smith, senior director of strategic marketing at Synopsys Inc. Smith called version 3.1 "the strong foundation that enables designers and vendors to start using the new standard." The enhanced version 3.1a "expands on that foundation by adding some new capabilities," he said.
Changes that are expected in SystemVerilog 3.1a include improvements in global declarations and separate compilation, a...