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Abstract

The DICE flip-flop has been rendered ineffective in deep-submicron technology nodes (e.g. 65 nm and 28 nm) due to charge sharing when exposed to single event strikes. This paper presents a new single event upset tolerant flip-flop design by applying the hardening technique on DICE at the layout level. This approach is an alternative to existing Layout Design through Error-Aware Transistor Positioning (LEAP); it also re-places transistors in master and slave DICE latches in the zigzag fashion in the layout. Both computer simulations and heavy-ion experimental results demonstrate that our proposed layout design has no single event upset errors under normal strikes until LET = 37 MeV·cm2/mg compared to the traditional DICE structure.

Details

Title
A Layout-Based Rad-Hard DICE Flip-Flop Design
Author
Wang, Haibin 1   VIAFID ORCID Logo  ; Dai, Xixi 2 ; Younis Mohammed Younis Ibrahim 2 ; Sun, Hongwen 2 ; Nofal, Issam 3 ; Cai, Li 4 ; Guo, Gang 4 ; Shen, Zicai 5 ; Chen, Li 6 

 College of IoT Engineering, Hohai University, Changzhou, China; College of Engineering, University of Saskatchewan, Saskatoon, Canada; Innovation Foundation of Radiation Application, China Institute of Atomic Energy, Beijing, China 
 College of IoT Engineering, Hohai University, Changzhou, China 
 iRoC Technologies, Grenoble, France 
 Innovation Foundation of Radiation Application, China Institute of Atomic Energy, Beijing, China 
 Beijing Institute of Spacecraft Environment Engineering, Beijing, China 
 College of Engineering, University of Saskatchewan, Saskatoon, Canada 
Pages
111-117
Publication year
2019
Publication date
Feb 2019
Publisher
Springer Nature B.V.
ISSN
0923-8174
e-ISSN
1573-0727
Source type
Scholarly Journal
Language of publication
English
ProQuest document ID
2168405143
Copyright
Journal of Electronic Testing is a copyright of Springer, (2019). All Rights Reserved.