Analytical Review of Noise Margin in MVL: Clarification of a Deceptive Matter

Abstract

Multiple-valued logic (MVL) can lead to fewer interconnections inside and outside a chip. It can also increase computational performance. Despite these intrinsic advantages, MVL circuits are more prone to noise than the binary counterparts. Since the voltage range is divided into some narrow zones, it is essential to consider noise margins carefully when designing MVL circuits in order to make certain of their suitability and adequate reliability. Several ternary and quaternary inverters, whose voltage transfer characteristics (VTC) suffer from reduced noise margins, have been presented in the literature. This shows that further clarification is definitely required. In this paper, the correct VTC curve of a ternary inverter with proper attributes is clarified. The explanations go beyond ternary logic to cover quaternary and other MVL systems as well. Then, the paper undertakes a review of noise margin and static noise margin measurements for some well-known ternary and quaternary inverters. Besides, the effects of process variation on noise margin are studied.