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Network processors are designed for speed, but progamming them is often a challenge. Here, you'll find the information you need to write software that makes the most of them.
Network processors are specialized CPUs optimized to support the implementation of network protocols at the highest possible speed. The overarching emphasis on speed results in unconventional hardware architectures that create new challenges for the software engineer.
This article discusses the forces that influence the design of software running on and communicating with network processors. It also explores why network processors are needed and examines the common multiprocessor architectures underlying the variety of network processors. In it, I will discuss software architectures that are effective for network processors, and look at functionality implemented in network processor software, as well as network processor programming languages. I will address the challenge of portability and the role of industry standards in meeting that challenge. Finally, I will highlight the impact of network processors on the architecture of surrounding software such as protocol stacks.
Where are network processors used?
A network processor is used in a network traffic manager, which occupies the space between a network interface and a switch fabric in a switcher/router. The traffic manager decides where, when, and how incoming and outgoing data will be sent next. It strips, adds, and modifies packet headers. It also makes routing and schedule decisions. The traffic manager has interfaces to the network and to the switch fabric. In Figure 1, these are labeled PHY (physical interface) and CSIX (common switch interface) respectively.1
Early traffic managers were built around a general purpose processor (GPP). The GPP was supported by a direct memory access controller (DMAC) and simple I/O devices. Traffic was transferred in protocol data units (PDUs) between memory and the switch fabric or network interface.2 The GPP accessed each PDU and programmed the peripheral devices to dispose of it, as shown in Figure 2.
This architecture changed as network speed outpaced processor and bus speed. The switch fabric interface and network interface were integrated into a single application-specific integrated circuit (ASIC) to allow PDUs to be transferred without passing over the system bus. This is illustrated in Figure 3.
This new architecture meant that control of individual PDUs was...