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Abstract

Dedicated hardware can be employed to release the central processing unit (CPU) of an image processing system of routine image preprocessing tasks, thereby increasing the operational speed of the system. The hardware implementation of a one-pass fill, shrink, and expand algorithm to clear random noise from an image is presented. The algorithm's 3 operations (fill, shrink, and expand) operate in parallel on a raster-scan image in a pipelined system. Simulation results are given, and the operating speed and cost are compared with those of a multiprocessor system using 8086. The maximum speed of the system, 25 X 10 to the 6th power pixels/second, is more than adequate for real-time operation on pictures from a conventional television camera. The overall component cost of the system is calculated to be only $5.00. In contrast, a multiprocessor system using the 512 Intel 8086 processors and costing $134,000 can perform the operations at a maximum speed of 2.9 X 10 to the 6th power pixels/second.

Details

10000008
Title
Hardware Implementation of a Parallel Noise Clearing Algorithm
Publication title
Volume
26
Issue
2
Pages
119
Number of pages
10
Publication year
1989
Publication date
Jun 1989
Publisher
Elsevier Sequoia S.A.
Place of publication
Amsterdam
Country of publication
Switzerland
ISSN
01656074
CODEN
MMICDT
Source type
Scholarly Journal
Language of publication
English
Document type
PERIODICAL
Accession number
00455553
ProQuest document ID
218895982
Document URL
https://www.proquest.com/scholarly-journals/hardware-implementation-parallel-noise-clearing/docview/218895982/se-2?accountid=208611
Copyright
Copyright Elsevier Sequoia S.A. Jun 1989
Last updated
2024-12-01
Database
ProQuest One Academic