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Many excellent PLLs require a +5 volt or lower supply. Since the widest-band VCOs need a considerably higher maximum tuning voltage, amplification is required. This article describes, by example, the design of such a circuit, with emphasis on minimum phase noise degradation.
Example
The Micronetics MW500-1364 VCO covers 5.4 - 6.3 GHz with a maximum required tuning voltage (V^sub t^) range of +1.0 to +16.8 V.
An Analog Devices AD797 op amp will be used for its very low noise, only 0.9 nV/root at 25[degrees]C (the open-ckt. Noise of a 50 ohm resistor). Starting with Figure 1, the necessary order of design will be shown.
1. Minimum resistor values (for lowest noise) permitted by op amp current: starting with R2, at maximum VCO V^sub T^ = 16.8 V, op amp input pins are at +4.5 V (from PLL). The AD797 data shows 30 mA minimum limit. So, minimum R2 = (16.8 V - 4.5 V) / 30mA = 410 ohm
A value of 475 ohm will be selected, to allow some margin.
Maximum R2 dissipation = 0.319 W; a 0.4 W 1% resistor is used.
2. Gain required = (16.8 V - 1.0 V) / (4.5 V - 0.5 V) = 3.95 = 1 + R2/R1
R1 (maximum) - 161 ohm, nearest 1% value = 162 ohm Note: Addition of a biasing resistor (shown later) will slightly increase gain, affording some margin with R1 = 162ohm.
3. Biasing to center available output range: At the PLL range center (2.5 V), the output in Figure 1 is 9.83 V. Desired V^sub T^ range center is 8.9 V. Thus, the output should be shifted by an offset of -0.93 V. As shown later, supplies of +22 V...