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A technique for minimizing the test-application time of a circuit board designed with boundary scan is presented. The technique is based on the use of multiple boundary scan paths. The test application time that can be achieved with this technique is compared with test application times for boards with a single boundary-scan path. It is pointed out that the test application time reduction depends on the board organization characteristics, specifically on the distribution of chips into groups. The proposed approach also has the potential of reducing the test evaluation time, that is, fault detection and isolation, by taking advantage of the parallel test-response of many identical chips. The analytical results obtained are applied to a real board design used for demonstration purposes. The test application time speed-up is found to be consistent with the claims of the proposed approach and almost linearly dependent on the number of scan paths used.