A generic hardware architecture to support the system level synthesis of digital systems

Abstract

A generic hardware structure, which is the target for a system level VLSI synthesis system, is described. The specification of a real-time control system is defined, in the language BEADLE, as a logical network of concurrently active sequential tasks that synchronize to communicate. The architecture was designed to implement such specifications using a number of node processors, one per task, interconnected via a customized communications network. The novelty of the approach is that the generic architecture is personalized by a high-level synthesis system for an application. The resulting hardware architecture is defined in VHDL and is used as an input to lower-level physical synthesis tools. The relationship between the BEADLE language and the generic architecture is described, along with details of how the architecture is customized for specific applications.