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The IBM logic-based eDRAM (embedded DRAM) technology integrates a trench DRAM (dynamic random access memory) storage-cell technology into a logic-circuit technology, merging the two previously separate technologies. Since its introduction in the 1970s, the DRAM technology has been driven by cost while the logic technology has been driven by speed, leading to an everwidening gap between slower memory and faster logic devices. That has led to the need for increasingly complex levels of memory hierarchies, resulting in considerable degradation of system performance despite many design and architecture compromises. DRAM can provide six to eight times as much memory as SRAM (static random access memory) in the same area, but has been too slow to be used at any cache level. Our studies, highlighted in this paper, indicated that the use of logic-based DRAM could resolve that difficulty-and was necessary for integrating systems on a chip. This has led to the inclusion of logic-based eDRAM as a memory option in the IBM ASICs (application-specific integrated circuits) product.
Introduction
The principles on which the logic-based eDRAM advantages are based are easy to understand. Most important is that the density advantage of DRAM permits replacement of the same area of SRAM with DRAM, which is from four times up to as much as eight times larger in capacity [1]. A factor of 16 to 20 or more in DRAM vs. SRAM capacity per unit area is obtained if DRAM is designed, in the traditional way, for achieving optimum density. The factor decreases to approximately 4 to 8 when the DRAM is designed for improved speed because of the need for shorter bits lines, faster sensing, etc. For cache applications, such as for an L2 cache, the miss ratio decreases approximately as the square root of the capacity increase. Hence, the use of a cache that is larger by a factor of 4 leads to a decrease in the miss ratio by a factor of 2; some relevant studies are described later. Fewer misses to an on-chip cache result in a decrease in the number of cache reloads needed from the slower, external (off-chip) memory system. The larger-capacity on-chip DRAM may not provide a performance improvement if the access speed is too slow. However, the DRAM need not...