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Processor Local Bus (PLB)
General processor local bus
Synchronous, nonmultiplexed bus
Separate Read, Write data buses
Supports concurrent Read, Writes
Multimaster, programmable-priority, arbitrated bus
66/133/183 MHz (32-/64-/128-bit)
32-bit address
32-/64-/128-bit implementations (to 256-bit)
Pipelined, supports early split transactions
Overlapped arbitration (last cycle)
Supports fixed, variable-length bursts
Bus locking
On-Chip Peripheral Bus (OPB)
Peripheral bus for slower devices
Synchronous, nonmultiplexed bus
Multimaster, arbitrated bus
32-bit address
Separate 32-bit Read, Write buses
Pipelined transactions
Overlapped arbitration (last cycle)
Supports bursts
Dynamic bus sizing, 8-, 16-, 32-bit devices
Single-cycle data transfers
Bus locking (parking)
Device Control Register (DCR) Bus
Provides alternate path to device control registers
Synchronous, nonmultiplexed bus
Separate Read, Write data buses
Single-master, multiple-slave bus
10-bit address bus
32-bit data buses
Two-cycle minimum Read/Write cycles
Distributed multiplexer architecture
Supports 8-, 16-, 32-bit devices
Single-cycle data transfers
Overview
System-on-a-chip (SoC) and ASIC silicon densities now support system-level implementations. The buses to link processors, memory, peripherals, and special functions are necessary. On-chip multilevel bus systems have emerged to meet these needs. One is the CoreConnect on-chip bus system from IBM Microelectronics. Originally designed to support PowerPC cores for IBM ASICs, this bus system now handles other processors and can be licensed for deployment. It's a major contender to Silicore's Wishbone (www.silicore.com), ARM's AMBA (www.arm.com), and other multilevel bus systems.
CoreConnect is an on-chip silicon bus for an ASIC or FPGA designs. It consists of a three-level system: the processor local bus (PLB), the on-chip peripheral bus (OPB), and the device control register (DCR) bus. The first bus, the PLB, connects the processor to high-performance peripherals, such as memory, DMA controllers, and fast devices.
Bridged to the PLB, the OPB supports the slower-speed peripherals. The third bus, the DCR, is a separate control bus that links to all of the devices, controllers, and bridges. It provides a separate path to set and monitor the individual control registers.
Processor Local Bus