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Abstract

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TransEDA's Assertain is billed as a "verification closure-management tool." But it's also a way to derive metrics that can tell users when their verification process is truly complete. Assertain monitors, measures, and manages the verification process in one integrated environment.

Details

1007133
Subject
Design engineering;
Software packages;
Electronic design automation;
Manyproducts;
Integrated circuits;
Automation;
Product introduction;
Operating systems;
Design;
Designers
Business indexing term
Location
United States--US
Company / organization
Name:
Actel Corp
NAICS:
334118, 334413;
Name:
TransEDA
NAICS:
511210;
Name:
Agilent EEsof EDA
NAICS:
513210;
Name:
CriticalBlue
NAICS:
513210
Product name
Actel Libero IDE 6.2, Agilent EEsof EDA Momentum ADS 2005A, Agilent EEsof EDA Momentum RFDE 2005A, CriticalBlue Cascade, TransEDA Assertain
Classification
9190: United States
7500: Product planning & development
8302: Software & computer services industry
Title
FPGA Tool Suite Adds Native Static Timing Analysis
Author
Maliniak, David
Publication title
Electronic Design; Nashville
Volume
53
Issue
16
Pages
32
Number of pages
1
Publication year
2005
Publication date
Jul 21, 2005
Section
TechView: EDA
Publisher
Endeavor Business Media
Place of publication
Nashville
Country of publication
United States
Publication subject
Engineering--Electrical Engineering, Engineering
ISSN
00134872
e-ISSN
19449550
CODEN
ELODAW
Source type
Trade Journal
Language of publication
English
Document type
News
Document feature
Illustrations
ProQuest document ID
220999636
Document URL
https://www.proquest.com/trade-journals/fpga-tool-suite-adds-native-static-timing/docview/220999636/se-2?accountid=208611
Copyright
Copyright Penton Media, Inc. Jul 21, 2005
Last updated
2024-11-26
Database
ProQuest One Academic