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TechView: EDA
Cadence's new verification platform provides native support for high-level languages and transaction-level virtual prototypes.
Verification of systems-on-a-chip (SoCs) is hard and getting harder. Not only are today's verification flows fragmented, but the flows are cumbersome. With more than 70% of silicon re-spins containing functional errors these days, verification clearly remains a bottleneck.
In rolling out its Incisive verification platform, Cadence brings together a unified methodology based on a single-kernel architecture that can compress overall verification cycles by as much as 50%. Almost as importantly, the platform provides native support for Verilog, VHDL, SystemC, the SystemC Verification Library, the Sugar property specification language, algorithm development,...