ASIC Verification Technology Brings Bugs To Their Knees

Abstract

To employ Total Recall technology, users would specify a block or full chip for debugging. All memory, logic, and associated circuitry is surrounded by control logic and stimulus. That stimulus is delayed by a specified number of clocks, and all assertions in the HDL are synthesized into the control logic. The design is then loaded into an FPGAbased prototyping board and run as though in emulation.

In an ideal world, ASIC verification would combine the bug visibility of simulation with the speed of FPGA prototype- based techniques. Synplicity's Total Recall technology is an attempt to achieve just that.

Total Recall technology allows the capture of all signals within a design (either a module or full chip), including memory states, across a user-defined number of cycles prior to the point at which a trigger condition is met or an assertion fires. The complete design state, along with an automatically generated testbench, then can be exported to a hardware description language (HDL) simulator, where the sequence of events can be replayed as many times as it takes to understand and repair a problem (see the figure).

To employ Total Recall technology, users would specify a block or full chip for debugging. All memory, logic, and associated circuitry is surrounded by control logic and stimulus. That stimulus is delayed by a specified number of clocks, and all assertions in the HDL are synthesized into the control logic. The design is then loaded into an FPGAbased prototyping board and run as though in emulation.

When either an assertion fires or a breakpoint is hit, the replicated design would reset to the specified number of clock cycles earlier than that point. The initial state and auto-generated testbench is moved to the HDL simulator, where the designer can run forward to the point that the problem developed and see what led up to it.

The ability to "instrument" the register transfer level (RTL) with synthesized assertions is a crucial feature that makes assertions much easier to use as they are intended. The added benefit is that the designer's own assertions can be used to full advantage, rather than those assertions that might be added later by verification engineers who are less familiar with intent of the design.

Total Recall technology works for nondeterministic bugs found in live, running hardware. In such cases, the combination of Total Recall technology with FPGA-prototype speeds will capture full design visibility before and after the bug is triggered, giving users the full environment and data they need to verify bug fixes.

Synplicity plans to incorporate Total Recall technology into upcoming versions of its ASIC verification tools.

Synplicity Inc.

www.synplicity.com

ED ONLINE 14594

Sidebar

With Synplicity's Total Recall technology, all signals within a design are captured from a user-defined number of cycles before an error occurs. The full design state then can be exported to an HDL simulator for examination.