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In an ideal world, ASIC verification would combine the bug visibility of simulation with the speed of FPGA prototype- based techniques. Synplicity's Total Recall technology is an attempt to achieve just that.
Total Recall technology allows the capture of all signals within a design (either a module or full chip), including memory states, across a user-defined number of cycles prior to the point at which a trigger condition is met or an assertion fires. The complete design state, along with an automatically generated testbench, then can be exported to a hardware description language (HDL) simulator, where the sequence of events can be replayed...