Content area

Abstract

Batch-processing machines can process several jobs simultaneously. These machines are commonly used to test Printed Circuit Boards (PCBs). The processing time and the dimensions of the PCB are given. Each batch is formed such that the total size of all the PCBs in the batch does not exceed the machine capacity. The batch processing time is equal to the longest processing time of all the PCBs in the batch. These batch processing machines are expensive and a bottleneck. Scheduling PCBs on these parallel batch processing machines to minimize their makespan is NP-hard. Consequently, we propose several heuristics. The performance of the proposed heuristics is compared to a simulated annealing approach and a commercial solver.

Details

Title
Heuristics to minimize makespan of parallel batch processing machines
Author
Damodaran, Purushothaman 1 ; Ping-Yu, Chang 2 

 Department of Industrial and Systems Engineering, Florida International University, Miami, FL, USA 
 Department of Industrial Engineering and Management, Mingchi University of Technology, Taipei, Taiwan 
Volume
37
Issue
9-10
Pages
1005-1013
Publication year
2008
Publication date
Jun 2008
Publisher
Springer Nature B.V.
Place of publication
Heidelberg
Country of publication
Netherlands
ISSN
02683768
e-ISSN
14333015
Source type
Scholarly Journal
Language of publication
English
Document type
Journal Article
Publication history
 
 
Online publication date
2007-05-09
Milestone dates
2007-04-05 (Registration); 2006-12-12 (Received); 2007-04-05 (Accepted)
Publication history
 
 
   First posting date
09 May 2007
ProQuest document ID
2262477074
Document URL
https://www.proquest.com/scholarly-journals/heuristics-minimize-makespan-parallel-batch/docview/2262477074/se-2?accountid=208611
Copyright
The International Journal of Advanced Manufacturing Technology is a copyright of Springer, (2007). All Rights Reserved.
Last updated
2019-07-24
Database
ProQuest One Academic