Building A Pipelined Computer In The Architecture Laboratory

Abstract

This computer architecture laboratory uses an object-oriented approach to provide a simulation modeling language. This language allows students to complete models of real pipelined computers. The modeling language is implemented as a class library for C++. Using this library, students are able to complete working models of an actual Silicon Graphics microprocessor, the MIPS 4000. Student work is easily validated since a correct model allows simulated execution of the code produced for a standard model of the microprocessor.

Introduction Students come to this Computer Architecture course with a two-semester background in C++ programming, and one semester of introductory machine organization and assemble-language programming. The latter course, using the text by Maccabe [1], includes four laboratory sessions in which students use the digital simulator described below to implement combinational gating networks and simple sequential machines. The laboratory activity reported here supports this Computer Architecture course and is a required course for Computer Science and Computer Engineering majors, and is elected by many Electrical Engineering and other students. The course is completed by 60 students each semester. This course uses the text by Patterson and Hennessy [2] with supplementmy material from the MIPS Micro- processor User’s Manual [3]. Although each student is completing a functionally equivalent microprocessor, each is assigned person- alized data-flow pathways for which their component interconnections and control must be customized. The Pipelined Computer To accommodate the design and implementation of complex digital networks and computing structures, laboratories are turning to simulation, [4,5]. Simulation allows the convenient modeling of extensive designs. In keeping with the architecture of all modem computers, those implemented in this laboratory use pipelining for efficient execution of instructions. The figure shows the three stages, fetch, decode and execute, that are implemented.

completions are accomplished within each of

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