It appears you don't have support to open PDFs in this web browser. To view this file, Open with your PDF reader
Abstract
Comparatorsareone of the basic devices that is mostly used in analog-to-digital converters (ADC). Designing low-power circuits with CMOS technology has been a serious research problem for several years. Nowadays the need of low power electronics became vital in various fields. In this paper, stacking technique is used to reduce the power consumed by the comparator.65nm CMOS process is used to design and simulate the comparator. The power consumption ofproposed comparator is compared with thepower consumption of double tail dynamic latch comparator. The proposed approach obtained less power consumption results.
You have requested "on-the-fly" machine translation of selected content from our databases. This functionality is provided solely for your convenience and is in no way intended to replace human translation. Show full disclaimer
Neither ProQuest nor its licensors make any representations or warranties with respect to the translations. The translations are automatically generated "AS IS" and "AS AVAILABLE" and are not retained in our systems. PROQUEST AND ITS LICENSORS SPECIFICALLY DISCLAIM ANY AND ALL EXPRESS OR IMPLIED WARRANTIES, INCLUDING WITHOUT LIMITATION, ANY WARRANTIES FOR AVAILABILITY, ACCURACY, TIMELINESS, COMPLETENESS, NON-INFRINGMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Your use of the translations is subject to all use restrictions contained in your Electronic Products License Agreement and by using the translation functionality you agree to forgo any and all claims against ProQuest or its licensors for your use of the translation functionality and any output derived there from. Hide full disclaimer
Details
1 Dept. of ECE, KoneruLakshmaiah Education Foundation, Guntur, AP, India