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Abstract
With the development of the Internet of Things, low-power technology has gradually become a primary factor in processor design. Processor sleeping mode is considered as an effective low-power technique. However, operation errors may occur if the long cycle instruction has not been completed during sleeping mode switch. To solve this problem, a novel sleep scheduling strategy based on RISC-V instruction set architecture is proposed. In this paper, the structure of RISC-V processor with task dispatching mechanism is described firstly. Then, WFI instruction and gating clock technology are adopted to realize the sleep scheduling strategy. Finally, hardware simulation is executed to demonstrate the feasibility of the novel sleep scheduling strategy.
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Details
1 Key Laboratory of Agricultural Information Standardization, Ministry of Agriculture and Rural Affairs, China Agricultural University, Beijing 100083, China; College of Information and Electrical Engineering, China Agricultural University, Beijing 100083, China
2 Institute of Semiconductors, Chinese Academy of Sciences, Beijing, China; Center of Materials Science and Optoelectronics Engineering, School of Microelectronics, University of Chinese Academy of Sciences, Beijing, China