Timing analysis journey from OCV to LVF

Abstract

In the present era, robust, reliable, and efficient SOCs are the need of the hour due to the rapid growth of IoT, networking, artificial intelligence, and many newer technologies. There is huge competition in the market to decrease the size of the electronic devices. All these market demands have put lots of pressure on silicon industries to accommodate more functionality on a single chip. As a result of this, with time, there is very fast shrinkage in the technology node. But this technology advancement comes with plenty of challenges. One of the primary challenges is undesired on-chip local variations (OCV) & its accurate modeling for timing analysis (STA). This paper discusses all the aspects of timing analysis and the evolution of different methodologies that shape timing analysis over the course of time. The methodologies to define margins for accurate timing analysis is the heart of accurate analysis at lower nodes. The paper will include an emphasis on how the timing analysis have moved from a global derate value to the architecture, condition-based derate value, used through all these methodologies. The paper will focus on the concept of all of the important methodologies and how they have evolved through time.