Understanding the Origin of the Hysteresis of High-Performance Solution Processed Polycrystalline SnO2 Thin-Film Transistors and Applications to Circuits

Abstract

Crystalline tin oxide has been investigated for industrial applications since the 1970s. Recently, the amorphous phase of tin oxide has been used in thin film transistors (TFTs) and has demonstrated high performance. For large area electronics, TFTs are well suited, but they are subject to various instabilities due to operating conditions, such as positive or negative bias stress PBS (NBS). Another instability is hysteresis, which can be detrimental in operating circuits. Understanding its origin can help fabricating more reliable TFTs. Here, we report an investigation on the origin of the hysteresis of solution-processed polycrystalline SnO₂ TFTs. We examined the effect of the carrier concentration in the SnO₂ channel region on the hysteresis by varying the curing temperature of the thin film from 200 to 350 °C. Stressing the TFTs characterized further the origin of the hysteresis, and holes trapped in the dielectric are understood to be the main source of the hysteresis. With TFTs showing the smallest hysteresis, we could fabricate inverters and ring oscillators.

1. Introduction

With the development of amorphous oxide semiconductor (AOS) electronics, various oxide-based semiconductors have been investigated. Indium gallium zinc oxide (IGZO) [1], indium zinc oxide (IZO) [2], indium gallium oxide (IGO) [3], zinc tin oxide (ZTO) [4], and indium zinc tin oxide (IZTO) [5] all have in common an amorphous phase, a conduction through s orbitals, optical transmittance of ~80% in the visible region, and offer a mobility of ~10 cm²/Vs [1].

Single cation-based oxides demonstrate a polycrystalline phase with higher mobilities. Zinc oxide (ZnO) [6], indium oxide (In₂O₃) [3], and tin oxide (SnO₂) [7] are among the most investigated materials. One of the most valuable metrics in TFTs is the mobility, and ZnO TFTs have demonstrated 40–70 cm²/Vs [6,8] while In₂O₃ TFTs [4] have demonstrated mobilities ~50 cm²/Vs. Even the crystalline form of IGZO (c-axis crystalline IGZO, the so called CAAC-IGZO) has attracted attention due to the TFTs reaching mobilities ~90 cm²/Vs [9,10]. For a few years now, tin oxide has regained attention. Devices comprising SnO₂ have demonstrated high mobility. Perovskite solar cells [11,12] and TFTs have been the main focus of research. TFTs have shown mobilities ranging from 40 to 147 cm²/Vs [13,14]. Even more recently, the amorphous phase of tin oxide [15,16] has demonstrated possible use in TFTs, reaching similar performances as the polycrystalline counterpart. Interestingly, in all these studies authors used a high-k dielectric as the gate insulator (ZrO₂, HfO₂, Al₂O₃)_, and a very thin channel layer (less than 10 nm).

With the use of high-k dielectrics [17], it is possible to obtain clockwise or anticlockwise hysteresis in the TFTs. The reasons are multiple, but shortly, in n-type based TFTs, the clockwise hysteresis can be resulting from the semiconductor (trapping of the electrons), while the anticlockwise from the gate dielectric (due to the movement of mobile ions for example) [18]. The anticlockwise behavior can be used in memory devices, while it can be detrimental for circuits. To fully understand the origin of the hysteresis (i.e., trapping of charge carriers, movement of mobile ions in the semiconductor or in the dielectric), measuring the hysteresis at slow and fast rates can help discriminate the origin.

We previously demonstrated that solution processed SnO₂ using SnCl₂ precursors could have various phases, and that the curing and annealing temperatures could impact significantly the various optical, electrical, and physical properties [19]. Here, we implemented the polycrystalline SnO₂ thin films fabricated at various T_curing temperatures (200, 280, and 350 °C) and a fixed annealing temperature (T_anneal = 350 °C). High mobility TFTs (over 100 cm²/Vs) are obtained and we studied the hysteresis behaviors of the polycrystalline SnO₂ TFTs (poly-SnO₂ TFTs). By varying the sweep rate and applying negative and positive bias stresses to the TFTs, we can clearly identify the origin of the hysteresis.

2. Materials and Methods

2.1. Fabrication of the Precursor Solutions

Solutions of HfO₂ (SnO₂) were made by mixing HfCl₄ (SnCl₂) into a mixture of acetonitrile (Ac) and ethyleneglycol (Etg). We used 35% of Ac and 65% of Etg in volume%. The HfO₂ (SnO₂) precursor solutions were stirred in a N₂ environment for 2 h (24 h) before use. The HfO₂ precursor solutions had a concentration of 0.2 M and the SnO₂ ones had a concentration of 0.2 M for the thin films, and 0.167 M for the TFTs.

2.2. Thin Film Fabrication and Analysis

The SnO₂ thin films were fabricated by spin-coating at 2000 rpm during 25 s. After spin-coating, the layer was subject to a curing at 100 °C for 5 min, and a second curing step at 200, 280, or 350 °C for 5 min. The coating was repeated once. We measured the Hall effect on a Ecopia HMS-3000. The samples had a van der Pauw configuration. The data was collected from 15 points. We used the Kα line (1.54 Å) for X-ray diffraction measurement to evaluate the crystallinity of the thin films. The surface roughness was evaluated by atomic force microscopy (AFM) by using a XE-7 from Park systems. The optical properties were evaluated by using an Scinco S4100. We measured X-ray photospectroscopy (XPS) with a Nexsa from ThermoFisher Scientific, by using the Al-Ka at 1486.6 eV as the X-ray source. Calibration was made with the carbon peak at 284.8 eV.

2.3. Thin Film Transistor Fabrication and Analysis

We fabricated poly-SnO₂ TFTs by first sputtering 40 nm Mo as the gate on glass. After patterning, we spin-coated the HfO₂ film. The coating was made at 2000 rpm for 25 s. The layer was then subject to a curing at 250 °C for 5 min, and UV treatment during 90 s. The deposition, curing, and treatment were repeated to obtain a 95 nm thick HfO₂ layer. The samples were then subject to annealing at 350 °C for 2 h in air. The precursor solution of SnO₂ was spin-coated at 4000 rpm during 25 s, and followed a curing step explained in the previous paragraph. After patterning, the TFTs were annealed at 350 °C for 2 h in air. We created via holes, sputtered and patterned IZO as the source/drain electrodes. Finally, a hot-plate annealing at 300 °C for 2 h and another hot-plate annealing step at 350 °C for 1 h were performed.

We measured the TFTs IV curves with a 4156 C semiconductor parameter analyzer. The TFTs had a width W and a length L of 50 and 10 μm, respectively. We evaluated the field-effect mobility in the linear region

(1)${\mathsf{\mu }}_{\mathrm{lin}}={\frac{\partial I_{\mathrm{DS}}}{\partial {\mathrm{V}}_{\mathrm{GS}}}|}_{{\mathrm{V}}_{\mathrm{DS}}=0.1\mathrm{V}}\times \mathrm{L}/({\mathrm{V}}_{\mathrm{DS}}\times \mathrm{W}\times \mathrm{Cox})$

where Cox is the HfO₂ capacitance.

The threshold voltage was evaluated at W/L $\times$ 10⁻¹⁰ A. The slope was evaluated as

(2)$\mathrm{S}.\mathrm{S}.=\frac{\partial {\mathrm{V}}_{\mathrm{GS}}}{\partial log{I}_{\mathrm{DS}}}.$

The various parameters were averaged over 25 TFTs. The various parameters are extracted from the transfer curve measured at fast measurement rate, from negative to positive voltage. The hysteresis was measured at V_DS = 0.1 V, with a fast and a slow measurement rate related to an integration time of 6.04, and 20 ms, respectively. The positive (negative) bias stress PBS (NBS) were measured by applying V_GS = 3 V (−3 V) during 1 h. We note that the capacitance of the hafnium oxide dielectric was 219 nF/cm² [15].

2.4. Circuit Fabrication

The inverter and ring oscillator followed the same process steps as the TFTs. The inverter had a load TFT with width and length of 50 and 6µm, respectively. The driving TFT had a width and length of 400 µm and 6 µm. The inverter had a depletion mode structure with the gate of the load TFT connected to the output.

The ring oscillator consisted of 11 of these inverters. The output of one is connected as the input of the following one. The last inverter being connected to the first inverter. A buffer inverter is put at the end of the ring oscillator to stabilize the measured output.

3. Results

3.1. Thin Film Analysis

Figure 1 shows the optical and crystalline properties of SnO₂. Figure 1a shows the extraction of the band gap from the Tauc plot [20]. The films with a T_curing of 200, 280, and 350 °C had a respective bandgap of 3.89, 3.94, and 3.94 eV. The films are adequate for application in invisible electronics [1]. Figure 1b shows the results of the XRD measurements. For all T_curing, the thin films demonstrate the crystalline structure. Peaks related to the (110), (101), (200), and (211) are all observed. They are located at 26.6°, 33.8°, 37.8°, and 51.8°, respectively, for the thin film with the T_curing of 280 °C.

We extracted the carrier concentration N and the Hall mobility µ_H according to their definition:

(3)${\mu }_{\mathrm{H}}=\frac{\left|{\mathrm{R}}_{\mathrm{H}}\right|}{\rho }$

(4)$\mathrm{N} =1/\left({\mathrm{R}}_{\mathrm{H}}e\right)$

where RH is the Hall coefficient, and $\rho$ the electrical resistivity.

For the SnO₂ film cured at 200, 280, and 350 °C, we observe an increase in the carrier concentration from 1.37 ± 0.19 to 4.28 ± 0.54 to 4.47 ± 1.20 × 10¹⁸ cm⁻³. The Hall mobility also increases from 1.56 ± 0.32 to 1.79 ± 0.67 and to 2.28 ± 0.92 cm²/Vs. The mobility increases with the carrier concentration as for oxide semiconductors which has been explained by the percolation conduction of the charge carriers [21]. Also, we note that the values match the trend previously reported for SnO₂ [19].

Figure 2 shows the surface morphologies of SnO₂ made at the different curing temperatures measured by AFM. The quality of the surface can be assessed by two metrics: the root mean square roughness (R_rms) and also the peak-to-valley roughness (R_pv). The respective R_rms roughness of SnO₂ cured at 200 (Figure 2a), 280 (Figure 2b), and 350 °C (Figure 2c) were 1.074, 0.725, and 0.844 nm and their respective R_pv values were 9.522, 5.778, and 8.092 nm. Therefore, curing SnO₂ at 280 °C (Figure 2b) leads to the smoothest surface. We note that we observe the crystallite sizes were in the 10–25 nm range, with the biggest crystallites for the 350 °C cured film. We note that the roughnesses decrease then increase at 280 °C. This was previously reported to be due to the melting of SnCl₂ at 250 °C [19], which would alter the crystallization of the 280 °C-cured thin films leading to a smoother surface.

3.2. Thin Film Transistor and the Origin of Their Hysteresis

The typical poly-SnO₂ TFT structure used in this work is shown at the bottom of Figure 3a. The micrograph of the TFT shown on top of Figure 3a reveals the various elements constituting the TFT. The hysteresis of the TFT transfer curves measured at fast and low rates, when SnO₂ was cured at 200, 280, and 350 °C are shown in Figure 3b–d, respectively. On average the TFTs made with a SnO₂ thin film cured at 200, 280, and 350 °C show a linear mobility of 86 ± 12, 90 ± 12, 110 ± 35 cm²/Vs; a V_th of −0.04 ± 0.05, 0.02 ± 0.12, −0.19 ± 0.14 V; and a subthreshold swing of 103.7 ± 9.9, 112.9 ± 9.4, and 102.7 ± 8.4 mV/dec. We note that the reliability of the extraction of the mobility in particular is highly depending on the size of the TFT [22]. The size chosen in the study should not have a significant impact on the mobility value [15,22]. We gather in Table 1 our present results and various other TFT performances using polycrystalline oxide semiconductors.

We note that even though the hysteresis is an important parameter, the characterization is only seldom reported.

At the T_curing of 200 and 280 °C, the hysteresis is clockwise, and the slow sweep rate measurements lead to higher hysteresis than the fast sweep rate measurements. We note that the slow sweep rate hysteresis for the 280 °C-cured-SnO₂ is smaller than the TFTs with the 200 °C-cured-SnO₂ layer. Also, the fast sweep measurement rate leads to a ~0.15 V hysteresis. At T_curing of 350 °C, an anticlockwise hysteresis is observed, and the fast sweep rate leads to higher hysteresis than the slow sweep rate. The reason why the TFT only shows the anticlockwise hysteresis will be discussed later.

A slow mobility species or a slow phenomenon responsible for the hysteresis for the 200- and 280 °C cured SnO₂ based TFT could be the reason for the slow sweep measurement rate leading to higher hysteresis than the fast measurement rate [18]. Also, the amount of the species would be smaller in the former than the later. The anticlockwise hysteresis is usually resulting from moving ions in the dielectric, from charge carriers entering the dielectric, or from the polarization of the dielectric. An anticlockwise hysteresis resulting from the polarization of the dielectric would have appeared in all conditions, and cannot therefore explain the behavior of our TFTs. Also, a clockwise hysteresis usually results from charge carriers near/at the channel/dielectric interface. To clarify the underlying phenomenon, we performed PBS and NBS on the TFTs, and measured the hysteresis.

3.3. Bias Stress Effect on Poly-SnO₂ Thin-Film Transistors

Figure 4a–f show the variation in the hysteresis under NBS (PBS) for TFT using SnO₂ having T_curing of 200 (Figure 4a,d), 280 (Figure 4b,e), and 350 °C (Figure 4c,f), respectively. As shown in Figure 4a–c, all curves shift negatively under NBS. Interestingly, the direction in the hysteresis changes in the 280 °C-cured SnO₂ based TFT from clockwise to anticlockwise (Figure 4b). Besides, the hysteresis becomes close to 0 V for the 200 °C-cured SnO₂ TFT. Not only did we consider the change in the transfer curve (the I_DS curve), we also considered the evolution of the gate leakage current (the I_GS curve). Under NBS, I_GS increases by almost an order of magnitude in all TFTs. The anticlockwise hysteresis appearing under NBS suggests that holes could enter the dielectric during the stress.

Figure 4d,e show that the 200- and 280 °C-cured SnO₂ TFT have a positive shift and a decrease in the current under PBS. Also, we observe the decrease of I_GS in Figure 4d,e. The decrease in the I_GS is almost one order of magnitude for the 200 °C-cured TFT. For the 350 °C-cured TFT, we observe that the TFT current decreases without a significant change in the V_th. Therefore, considering the various stresses and the various change in V_th and the change in I_GS, we understand that charge carriers are injected from and to the dielectric.

We therefore evaluated the band offsets between SnO₂ and HfO₂ for all three different curing temperatures of SnO₂ [26]. The valence band offset ΔE_v is defined as

ΔEv = (E_Hf4f − E_VBM)_HfO2surface − (E_Sn3d5/2 − E_VBM)_SnO2surface − (E_Hf4f − E_Sn3d5/2)_SnO2/HfO2, (5)

where HfO_2surface, SnO_2surface and SnO₂/HfO₂ denote, respectively, the top of the HfO₂ layer without SnO₂ on top of it, the top of the SnO₂ layer, and the HfO₂/SnO₂ interface.

Therefore, for each curing temperature we extracted the following peak values: the Hf 4f peak at the SnO₂/HfO₂ interface (as shown in Figure 5a,e,i), the Sn 3d_5/2 peak at the SnO₂/HfO₂ interface (as shown in Figure 5b,f,j), the Sn 3d_5/2 peak on the top of the SnO₂ layer (Figure 5c,g,k), and the valence band at the top of the SnO₂ layer (as shown in Figure 5d,h,l). The various extracted values are gathered in Table 2. We note that the values for the position peaks taken for HfO₂ without SnO₂ on top are taken from a previous report [16] and we consider the Hf 4f peak position E_Hf4f = 18.15 eV, the bandgap of HfO₂ Eg_HfO2 = 5.34 eV, and the position of the valence band E_VBM = 2.4 eV.

We could evaluate that the valence band offset was 0.17, 0.19 and 0.09 eV for the 200- 280- and 350 °C-cured SnO₂ layer, respectively. To avoid charge carrier injection, the offset value should be bigger than 1 eV [27]. So, our TFTs having a smaller band offset could have holes injected into the dielectric.

The small offset can therefore explain the possibility of holes to be trapped into (detrapped from) the dielectric under NBS (PBS). The presence of trapped holes in the dielectric would add up to the electric field attracting more electrons in the channel resulting in an anticlockwise hysteresis. Under PBS, holes can exit the dielectric leading to a decrease in the gate leakage, but also a decrease in the electron current. Thus, trapping of electrons would lead to the observed clockwise hysteresis.

The fact that only the 350 °C-cured SnO₂ TFT demonstrate the anticlockwise hysteresis could result from the higher density of holes in the SnO₂ layer compared to the other temperature cured SnO₂ layer based TFTs. Also, the TFT cured at 350 °C showed an apparent higher mobility. But this value is certainly due to the presence of injected holes in the gate insulator increasing the electron density in the channel during operation and therefore leading to an increased value of the mobility. We note that the 280 °C-cured-SnO₂ layer showing the smallest R_RMS and R_pp value leads to the TFT with the smallest clockwise hysteresis. As mentioned before, we previously studied the fabrication of SnO₂ thin films at various curing and annealing temperatures [19]. We demonstrated that the melting of the precursors at 250 °C had an impact on the various properties of the thin films. The various films had an increase of the R_rms roughness and R_PV for temperatures higher than the melting temperature. The TFT properties are consistent with the thin film fabrication process and their properties.

Also, we note that holes should be moving slowly in SnO₂, as they would in IGZO with a mobility of ~0.01 cm²/Vs [28]. Under NBS, holes may be injected from the SnO₂ layer to the dielectric and be trapped, resulting in a negative shift and the anticlockwise hysteresis. This also explains the change of the hysteresis direction for the 280 °C-cured SnO₂ based TFT shown in Figure 4b. Therefore, we propose that the main phenomenon responsible for the hysteresis in our solution-processed SnO₂ TFT is the trapping of holes in the dielectric. Detrapping or trapping of holes would therefore monitor the hysteresis. Figure 6 shows the band offsets between HfO₂ and polycrystalline SnO₂ Figure 6a summarizes the bandgaps (3.89–3.94 eV for SnO₂, 5.34 eV for HfO₂), ΔE_v (0.09–0.19 eV), and ΔEc (deduced from the previous values). To find ΔE_v, we used the values taken from Figure 5, and gathered in Table 2. Figure 6b,c summarize the proposed mechanism of the hole extraction (injection) during PBS (NBS).

3.4. Application to Circuits: Inverters and Ring Oscillators

We fabricated both inverters and ring oscillators as circuits to demonstrate the possibility to incorporate SnO₂ TFT in more advanced circuitry. We chose the devices with a curing step at 280 °C. Indeed, the TFTs showed the clockwise hysteresis. Compared to the 200 °C cured TFTs, the 280 °C-cured TFTs demonstrated smaller hysteresis and higher mobility. We note that the ring oscillators using the TFTs with the anticlockwise hysteresis could not show any oscillation. Figure 7a,b show the respective schematics of an inverter and a ring oscillator (R.O.). The inverter output is shown in Figure 7c. At 5 V the gain is ~30 V/V. The top of Figure 7d shows the optical image of a fabricated ring oscillator, and its various components. In the figure, we indicated the basic inverter structure, but also the buffer. The bottom of Figure 7d shows the output of the R.O. at a V_dd of 3 V. The peak-to-peak voltage (V_pp) is 1.862 V, the frequency is 2.12 kHz. Even though the operating frequency is rather low, which could be due to the low sheet resistance of IZO (~20 ohm/$\square$), and the non-optimized ratio of the TFTs, the present results demonstrate the possibility to further include poly-SnO₂ TFTs in other more advanced circuitry.

4. Conclusions

We successfully fabricated solution processed polycrystalline SnO₂ TFTs. The SnO₂ thin films were fabricated at various curing temperature to obtain various carrier concentrations, ranging from ~10¹⁸ to ~4 $\times$ 10¹⁸ cm⁻³. The TFTs demonstrated a field effect mobility of ~100 cm²/Vs. We demonstrated that under stress the hysteresis present in the TFTs was due to the presence of trapped holes in the gate dielectric. We suggest that the trapping occurs due to the small valence band offset between SnO₂ and HfO₂. Nonetheless, we demonstrated the possibility of fabricating circuits with SnO₂ TFTs. The inverters demonstrated a gain of ~30 V/V and the ring oscillators operated at a frequency of 2.12 kHz at a V_DD of 3 V. Further optimization of the TFTs by increasing the valence band offset could lead to higher reliability and circuits with higher performances.

Author Contributions

Methodology, C.A.; writing—original draft preparation, C.A.; writing—review and editing, C.A. and J.J.; funding acquisition, J.J. All authors have read and agreed to the published version of the manuscript.

Funding

This research was supported by the Technology Innovation Program (or Industrial Development Strategic Technology Development Program (20010082, Development of low temperature patterning and heat treatment technology for light and thermal stability in soluble oxide TFT manufacturing)) funded by the Ministry of Trade, Industry & Energy (MOTIE, Korea).

Institutional Review Board Statement

Not applicable.

Informed Consent Statement

Not applicable.

Data Availability Statement

Data is within the text.

Conflicts of Interest

The authors declare no conflict of interest.

Publisher’s Note: MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Figures and Tables

Figure 1. Thin film properties of solution processed SnO2 cured at 200, 280, and 350 °C, and annealed at 350 °C. (a) The Tauc plot for the extraction of the optical bandgap. The inset shows the energy between 3.8 and 4.5 eV. (b) XRD patterns. The dashed lines with the respective colors show the extraction of the bandgap. The dashed blue lines in (b) are here to help identify the various positions of the main peaks.

Figure 2. Surface roughness of SnO2 as measured by AFM. The thin films were cured at (a) 200, (b) 280, and (c) 350 °C. The color scale is given on the right hand side of each figure.

Figure 3. TFT structure and initial IV characteristics. (a) the TFT micrograph (top) and the TFT structure (bottom). The transfer of the poly-SnO2 TFTs using a SnO2 layer cured at a Tcuring of (b) 200, (c) 280, and (d) 350 °C, respectively. The solid (dash) line refers to IDS (IGS) measured at VDS = 0.1 V. The arrows indicate the direction of the hysteresis.

Figure 4. Evolution of the hysteresis curve of SnO2 TFT under negative and positive bias stresses for a typical TFT with a SnO2 layer made at a Tcuring of (a,d) 200, (b,e) 280, (c,f) 350 °C, respectively. The solid (dash) line refers to IDS (IGS) measured at VDS = 0.1 V. Black arrows indicate the direction of the hysteresis in all graphs except in (b) where the red (blue) arrows indicate the direction of the hysteresis at the beginning (the end) of the stress. All stresses were during 3600 s. All hysteresis curves were measured under slow rates.

Figure 5. XPS analysis used for the calculation of the band offsets for the various SnO2 curing temperatures. (a,e,i) the Hf4f at the interface of SnO2/HfO2, (b,f,j) the Sn3d5/2 peak at the SnO2/HfO2 interface, (c,g,k) the Sn3d5/2 at the top of the SnO2 surface, (d,h,l) the valence band of SnO2 at the top of the SnO2 surface. The first second, and third line shows the peaks for the SnO2 thin film cured at 200, 280, and 350 °C respectively. The peaks and curing conditions are indicated within the figures. The red lines in each graph shows the value of the peak extracted and used for the calculation of ΔEv.

Figure 6. Band offsets of polycrystalline SnO2 and HfO2. (a) Measured band offsets by XPS, (b) hole injection into the SnO2 layer under PBS, (c) hole injection into the HfO2 layer under NBS.

Figure 6. Band offsets of polycrystalline SnO2 and HfO2. (a) Measured band offsets by XPS, (b) hole injection into the SnO2 layer under PBS, (c) hole injection into the HfO2 layer under NBS.

Figure 7. Circuits fabricated with solution processed polycrystalline SnO2 TFTs. The schematic of (a) an inverter and (b) a ring oscillator (R.O.). (c) The output curve of an inverter (top) and its gain (bottom). (d) The optical image (top) and the output curve of a R.O.

Figure 7. Circuits fabricated with solution processed polycrystalline SnO2 TFTs. The schematic of (a) an inverter and (b) a ring oscillator (R.O.). (c) The output curve of an inverter (top) and its gain (bottom). (d) The optical image (top) and the output curve of a R.O.

Table 1

A comparison of various TFT performances using polycrystalline oxide semiconductors and their processing conditions.

Polycrystalline Oxide Semiconductor	Process	Process Temperature(°C)	Gate Insulator	µ(cm2/Vs)	Hysteresis (V)	Vth(V)	S.S(mV/dec.)	Ref.
CAAC-IGZO	Mist-CVD	450	Al2O3	90.4	~0	1.5	86	[6]
CAAC-IGZO	Rf-sputtering	300	Al2O3/HfO2/Al2O3	39.4	N/A	−4.46	380	[7]
In2O3 *	Spin-coating	250	ZrO2	59.8 *	N/A	2.02	180	[23]
In2O3	Atomic layer deposition	300	Al2O3	41.8	~0.05	−0.8	100	[24]
ZnO	Spray-coating	350	Al2O3	39.26	N/A	0.58	167	[8]
ZnO	ALD	350	SiO2	43.2	N/A	18.7	N/A	[25]
SnO2	Solution process	450	Al2O3	96.4	~1	1.72	260	[13]
SnO2	Physical vapor deposition	400	HfO2	147	N/A	0.27	110	[9]
SnO2	Spin-coating	350	HfO2	90	~0.15	0.02	113	This work

* With Li doping.

Table 2

Summary of the peak positions used to extract the valence band offset. All peak positions are in eV.

	Top of SnO2 Surface			SnO2/HfO2 Interface
SnO2Tcuring (°C)	EVBM	ESn3d5/2	ESn3d5/2-EVBM	Sn3d5/2	EHf4f	Ehf4f-ESn3d5/2	ΔEv
200	3.6 (d)	486.78 (c)	483.18	486.08 (b)	18.48 (a)	−467.6	+0.17
280	3.94 (h)	487 (g)	483.06	486.32 (f)	18.82 (e)	−467.5	+0.19
350	4.08 (l)	487.31 (k)	483.23	486.25 (j)	18.68 (i)	−467.57	+0.09

The letters in the cells correspond to the peak and peak position shown in the letter-designated-subfigure of Figure 5.

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