Embedded FPGA Controllers for Current Compensation Based on Modern Power Theories

Abstract

This work compares the performance of two embedded FPGA controllers that can be used in Active Parallel Power Filters (APPF). Both controllers are validated through the FPGA-in-the-loop (FIL) technique, the algorithm’s synthesis is accomplished using the Quartus II^® platform, and the board used is from Altera^®—Cyclone IV DE2-115. The main difference between the controllers resides in the power theories used to obtain the currents for compensation. The results confirm that the FPGA is a suitable digital device for the parallel operation of multiple compensators and calculation stages, being a viable solution for the requirements imposed in the control of APPF. Furthermore, the effectiveness of the FIL technique for validating the operation of digital circuits and control systems is also confirmed. Finally, a comparison between the processing costs of each of the implemented power theories is presented to guide novel proposals.

1. Introduction

In addition to active power, electrical power systems supply energy for asymmetric and reactive loads. The greater the preponderance of these loads, the more the electrical system is required, resulting in higher distribution losses, voltage drop increase, and underutilization of the installed capacity [1,2,3,4].

Furthermore, with the advent of semiconductors, non-linear loads were introduced and spread all over the electrical system. These, in turn, generate current harmonics that deform the sinusoidal characteristic of the voltage at the point of common coupling, further impairing the grid power factor. In addition to having the same impacts as the reactive ones, they can cause failures in the system’s protection, generate resonances, increase maintenance costs, and reduce the average life of equipment [5,6].

Mainly found in industrial environments to obtain a better power factor, capacitor banks are used for reactive compensation. It is also common to install capacitor banks and reactors in transmission lines, in order to improve quality standards to supply electrical energy within those standards [7]. However, the use of passive banks does not consider the influence of unbalanced loads and non-linear loads on the insertion of harmonics in the electrical system and the consequent impact on the functioning of these compensation elements [8].

In this sense, new methodologies are proposed that allow analysis, monitoring, pricing, disturbance compensation, and responsible management of modern electrical systems. Among these methodologies, Active Parallel Power Filters (APPFs) have the objective of detecting and compensating the non-active current portions arising from reactive or non-linear loads and from the unbalance between the supply phases [9]. With compensation, the system source is only responsible for the active power portion, reducing technical and economic impacts arising from the non-active currents [10].

However, despite the APPFs presenting themselves as a viable alternative to instantaneous compensation, the employment of these devices faces two important obstacles: the calculation of the compensation currents and the implementation of power theories in embedded systems.

The first obstacle refers to the compensation currents; after all, conventional power theory is limited to the frequency domain and does not predict the behavior of non-linear loads. In this sense, modern power theories have been shown to be viable alternatives for the detection of the parcels to be compensated. Among them, the Instantaneous Power Theory (IPT) [11] is not subjected to describing the behavior of the electrical system by redefining the powers, but operating on other bases to facilitate its manipulation. Consequently, they are more restricted to the separation between active and non-active currents. On the other hand, the Conservative Power Theory (CPT) [12] presents new definitions for power calculus. By redefining the entire power calculus, it can be used to describe electrical circuits and power systems in a different mode than usual. It can be characterized as a more complete theory, as it also allows for the separation of each portion of power according to the electrical element that originated it. In this way, the analysis of the impact of the insertion of the different components can be carried out to provide more concise data on its real impact on the electrical system.

The second obstacle to overcome is related to the implementation of power theories in embedded systems, since the complexity of the mathematical operations and computational cost are impeditive factors to achieving good performance in different compensation scenarios. Due to these requirements, among the main digital devices for embedded logic, FPGAs (Field-Programmable-Gate-Arrays), have become a viable alternative. The FPGA has advantageous characteristics since it allows parallel processing of its data in addition to working at higher frequencies. Parallel processing allows the analysis and evaluation of different results simultaneously, and its processing time makes it ideal for embedded systems as it minimizes the delays inherent to digital implementation [13,14]. Additionally, the number of bits from either the acquired variables or the coefficients of a mathematical operation can be changed according to the needed precision, and its flexibility makes possible the implementation of complex control systems.

This work proposes to implement, validate, and compare the performance of an APPF whose compensation currents will be obtained from the IPT and CPT. For that, the FPGA-in-the-Loop (FIL) technique will be used, which consists of the communication between the simulator and the FPGA board. In this case, plant behavior is obtained from the simulator and the calculations of the theories and the APPF control are implemented in FPGA through a hardware description language using VHDL (VHSIC hardware description language) [15]. It is worth mentioning that this language describes the behavior and structure of a digital system, that is, the logic units of the FPGA board are rearranged and interconnected to organize themselves in the synthesized circuitry, being able to assume the most varied circuits, according to the synthesis stage [16,17,18,19]. It is also important to highlight that FIL is a crucial tool for prototyping, since the control techniques and other calculations necessary for the operation of the desired topology can be physically validated, without the need for the physical plant itself [20]. Additionally, aiming to guide novel proposals, this paper presents as a contribution a comparison between the processing costs of the implemented power theories.

For the comparison tests between the theories implemented in FIL, the description of the circuits was carried out in Quartus II^® software and the board used was from Altera^® (San Jose, CA, USA), Cyclone IV DE2-115. The simulation environment was MATLAB/Simulink^® (Natick, MA, USA).

2. System Overview

2.1. Simulator System Parameters

Figure 1 presents all the power and control circuits for the implementation of an APPF. Firstly, it is important to point out that all the power circuits are implemented in the MATLAB/Simulink^® platform, whereas all the calculations and control circuits are implemented in the FPGA board. At the top of Figure 1, there is an electrical circuit whose currents must be compensated. Basically, it consists of a three-phase voltage source with a grounded neutral and an unbalanced three-phase non-linear load. Just below, the APPF can be seen, which in this figure is divided into two parts. On the left, in the set called FIL, we can see the control circuit where the power theories and all the calculations are implemented. On the right, in the APPF block, the power circuit of the active filter can be observed.

Essentially, the APPF is a voltage source inverter, whose topology can be with three or four arms. In the case of this article, where a four-wire system is required to be compensated, a four-arm inverter is used, which is capable of compensating each of the phases and the neutral one. The capacitance C_f plays an important role in the circuit, being the voltage source that will allow current circulation in the inverter. Additionally, the APPF behaves like a current source since the inductances L_{f_a}, L_{f_b}, L_{f_c}, and L_{f_n} have their currents controlled based on the compensation references derived from the implemented power theories.

The FIL block is responsible for communicating the simulator software with the FPGA board. The three-phase supply voltages and currents, the filter inductance currents, and the inverter capacitance voltage are input data on the FPGA for the implementation of both theories and their controllers.

Due to FPGA speed, a switching frequency (f_s) of 400 kHz was chosen for the inverter. This characteristic is advantageous since the necessary filter inductances, observed in (1), are inversely proportional to f_s. In this way, the drastic reduction of the inductance values implies reduction in size and cost of the inductors that will be implemented. The usage of a higher switching frequency obligates the correct choice of semiconductors to maintain a desirable efficiency, with reduced conduction and commutation losses. In that sense, Silicon Carbide power switches (SiC) are good choices for future implementation [21]. Additionally, using 400 kHz of switching frequency the APPF can easily compensate harmonics up to the 40th.

(1)$L_{f\_\mu }=\frac{0.25\times V_{CC}}{2\times f_s\times \mathsf{\Delta }{i}_{máx}}.$

The C_f capacitance can be obtained by the reactive energy ($\Delta Q$) that this element can exchange in the system to compensate the active losses of the inverter and at the connecting elements (P_loss). Thus, through (2), and after mathematical manipulation, one can obtain (3). Frequency $\omega$ equals $3\times 2\pi f_g$, as it is a three-phase system. $\Delta V_{DC}$ is the allowed ripple voltage.

(2)$\Delta Q=P_{loss}=\frac{\Delta V_{DC}{}^2}{X_{Cf}}=\frac{\Delta V_{DC}{}^2}{1/\left(\omega \times C_f\right)}.$

(3)$C_f=\frac{P_{loss}}{\omega \times \Delta V_{DC}{}^2}.$

For the proper operation of the APPF, the C_f voltage must remain at a value higher than the line peak voltage, that is, a sufficient value for the modulation and control of the injected current, and remain constant during the converter’s operation. The chosen capacitance is 1.8 mF with 2% ripple at 125 W of compensation losses, aiming for 97.5% efficiency in a 5 kW application. The losses are low considering the usage of proper SiC Mosfets.

Table 1 summarizes the control parameters and physical elements of the proposed system. The loads to be compensated are shown in Table 2.

2.2. Control of the Inverter

To control the APPF, two loops are proposed: one for the current and other for the capacitor voltage. The converter transfer functions to be controlled by these loops are presented, respectively, in (4) and (5). They are obtained based on the converter topology using small-signal analysis [22].

(4)$G_i\left(s\right)=\frac{V_{CC}}{s\times L_f},$

(5)$G_v\left(s\right)=\frac{\sqrt{3}\times V_{LRMS}\times \sqrt{2}}{C_f\times s\times 2\times V_{CC}}.$

For the current loop, the crossing-over frequency ω_c was defined as ten times lower than f_s. For the control system, a proportional-integral (PI) compensator (C_i(s)) was designed with its zero positioned in the middle of ω_c. For the voltage loop, a crossing-over frequency of 1300 Hz was chosen for IPT and of 100 Hz for CPT, ensuring a dynamic response slow enough not to interfere with the current compensation. The adopted voltage controller (C_V(s)) was also a PI compensator.

Considering that the controllers must be discretized for FPGA implementation, the zero-order-hold analog-to-digital conversion method was used [23]. The chosen sampling time was 1 µs, minimizing problems with delays and preventing information loss during signal conversions. The APPF implemented in the simulation software runs with a sample time of 10 ns with a relative tolerance of 1 μs using the Ode-23tb solver—proper for power electronics applications. The values of voltage and currents are transferred from the simulator to the board at a 1 GHz rate, and the FIL was synchronized to acquire these data in the correct and fixed time step of 1 μs. For the controllers, the difference equation can be represented according to (6) [24], where x corresponds to the inputs, y to the outputs, g to the gains, and k to the sampling present time.

(6)$y\left(k\right)=g_{x1}x\left(k\right)+g_{x2}x\left(k-1\right)+y\left(k-1\right).$

Both analog and digital controller gains are summarized in Table 3.

Since the strategy to maintain the voltage on the capacitor is different for both theories, it was decided to use different gains in the voltage controllers.

In Figure 2, the control loops for the IPT are shown. In this figure, the voltage loop generates a power signal corresponding to what is necessary to keep the capacitor charged, which must be processed together with the powers used in the theory. Figure 3 shows the control loops for the CPT. In the external loop, which controls the capacitor voltage, the generated signal corresponds to a compensation current which is the result of the product between a phase reference and the voltage compensator output. $K_i$ and $K_v$ are considered unitary.

Precisely, due to the way the capacitor control reference is calculated, the outer voltage control in IPT theory is dynamically slower than in CPT theory. To rearrange the two theories with similar settling times for the capacitor voltage, adjustments were made to the gains, which resulted in the differences noticed in Table 3.

3. Power Theory

3.1. Instantaneous Power Theory

The IPT has, as proposed, the usage of the Clarke transform in the three-phase current and voltage signals [25,26]. According to (7), from a base change matrix, the a, b, and c axes are transcribed into the α, β, and 0 axes. In this transformation, the manipulation and determination of the instantaneous currents are simplified. Consequently, the separation of non-active from active currents is performed by determining the powers that effectively feed the loads. The base matrix is power invariant.

(7)$\left[\begin{array}{c}{u}_0\\ u_{\alpha }\\ u_{\beta }\end{array}\right]=\sqrt{\frac{2}{3}}\left[\begin{array}{ccc}\frac{1}{\sqrt{2}}& \frac{1}{\sqrt{2}}& \frac{1}{\sqrt{2}}\\ 1& \frac{1}{2}& \frac{1}{2}\\ 0& \frac{\sqrt{3}}{2}& \frac{\sqrt{3}}{2}\end{array}\right]\left[\begin{array}{c}{u}_a\\ u_b\\ u_c\end{array}\right].$

According to (8), the powers are divided into zero sequence, present in unbalanced systems with neutral conductor, real power, and imaginary power. Such powers can be separated into average and oscillating portions.

(8)$\left[\begin{array}{c}{p}_0\\ p\\ q\end{array}\right]=\left[\begin{array}{ccc}{v}_0& 0& 0\\ 0& v_{\alpha }& v_{\beta }\\ 0& v_{\beta }& -v_{\alpha }\end{array}\right]\left[\begin{array}{c}{i}_0\\ i_{\alpha }\\ i_{\beta }\end{array}\right].$

The real and zero sequence powers are associated with the energy consumed by the load; however, the great interest of compensation lies in allowing the power source to supply only the average real power. Thus, all zero-sequence power, imaginary, and real oscillating power are related to phenomena associated with unbalance, reactive loads, and non-linear loads. Therefore, the current responsible for all non-active content feeding the loads is calculated to be compensated by the APPF, and the power source will supply balanced, sinusoidal, and in-phase currents with the input voltage.

Something very important to consider is that the IPT allows for bidirectional power flow control. In the case of an APPF, the capacitance C_f must remain charged, that is, the system losses must be supplied. Consequently, in addition to the power portions to be compensated, the power to maintain C_f must be introduced for the calculation of the compensation currents (9).

(9)$\left[\begin{array}{c}{i}_{C_{\alpha }}\\ i_{C_{\beta }}\end{array}\right]=\frac{1}{v_{\alpha }^2+v_{\beta }^2}\left[\begin{array}{cc}{v}_{\alpha }& v_{\beta }\\ v_{\beta }& -v_{\alpha }\end{array}\right]\left[\begin{array}{c}\tilde{p}-p_{cap}\\ q\end{array}\right].$

Finally, through the inverse Clarke transform (10), the compensation currents are referenced in the a, b, and c axes, being available for the action of the current compensators.

(10)$\left[\begin{array}{c}{i}_{C_a}^{*}\\ i_{C_b}^{*}\\ i_{C_c}^{*}\end{array}\right]=\sqrt{\frac{2}{3}}\left[\begin{array}{ccc}\frac{1}{2}& 1& 0\\ \frac{1}{\sqrt{2}}& \frac{1}{2}& \frac{\sqrt{3}}{2}\\ \frac{1}{\sqrt{2}}& \frac{1}{2}& \frac{\sqrt{3}}{2}\end{array}\right]\left[\begin{array}{c}-i_0\\ i_{C_{\alpha }}\\ i_{C_{\beta }}\end{array}\right].$

3.2. Conservative Power Theory

The CPT works with new power concepts, allowing active compensation in both single and three-phase systems. Furthermore, it fully achieves compensation of the system currents even under unbalanced and non-sinusoidal power supplies [27,28].

Its main difference is the splitting of the powers between those derived from reactive and unbalances from those arising from current harmonics. Another contrast is found in the obtainment of reactive power as a non-conservative quantity since it depends on the frequency of the multiple harmonics of a signal. To overcome this difficulty, reactive power is presented and used together with active and residual power for active compensation.

In addition, the before-mentioned theory introduces the equivalent quantities responsible for defining the equivalence between phases for voltages, active power, and reactive energy. The average active power (P) is calculated as usual, and in a period T, it is the average value of the product of voltage and current in the m phases (11). To calculate the average reactive energy (W), the unbiased voltage $\widehat{v}\left(t\right)$ is used as shown in (12) and (13).

(11)$P= \frac{1}{T}{{\displaystyle \sum }}_{\mu =1}^m{{\displaystyle \int }}_0^{T}v{\left(t\right)}_{\mu }.i{\left(t\right)}_{\mu }dt,$

(12)$W= \frac{1}{T}{{\displaystyle \sum }}_{\mu =1}^m{{\displaystyle \int }}_0^T\widehat{v}{\left(t\right)}_{\mu }.i{\left(t\right)}_{\mu }dt,$

(13)$\widehat{v}{\left(t\right)}_{\mu }={{\displaystyle \int }}_0^{t}v{\left(\tau \right)}_{\mu }d\tau -\frac{1}{T}{{\displaystyle \int }}_0^{T}v{\left(t\right)}_{\mu }dt.$

With the view to obtain instantaneous power values, essential in compensation systems, the active power p(t) and the reactive energy w(t) can be obtained according to (14) and (15).

(14)$p\left(t\right)={{\displaystyle \sum }}_{\mu =1}^m{v}_{\mu }\left(t\right)i_{\mu }\left(t\right),$

(15)$w\left(t\right)={\displaystyle \sum }_{\mu =1}^m{\widehat{v}}_{\mu }\left(t\right)i_{\mu }\left(t\right).$

The instantaneous ($v_{eq}$) and effective ($V_{eq}$) values of the equivalent voltage and the instantaneous (${\widehat{v}}_{eq}$) and effective (${\widehat{V}}_{eq}$) values of the equivalent unbiased voltage are calculated according to (16) and (17).

(16)$v_{eq}=\sqrt{v_a^2+v_b^2+v_c^2}, V_{eq}=\sqrt{V_a^2+V_b^2+V_c^2},$

(17)${\widehat{v}}_{eq}=\sqrt{{\widehat{v}}_a^2+{\widehat{v}}_b^2+{\widehat{v}}_c^2}, {\widehat{V}}_{eq}=\sqrt{{\widehat{V}}_a^2+{\widehat{V}}_b^2+{\widehat{V}}_c^2}.$

The CPT proposes the separation of currents into active $(i_u^a)$, reactive $(i_u^r),$ and residual $(i_u^v)$ portions. Active currents (18)–(20) are separated into active balanced $(i_{\mu }^{ab})$ and unbalanced $(i_{\mu }^{au})$. Reactive currents (21)–(23) are split into reactive balanced $(i_{\mu }^{rb})$ and unbalanced $(i_{\mu }^{ru})$. Residual currents (24), or void, can be divided into scattered active and scattered reactive. These consider the different harmonics of the voltage and current signals, and in harmonics generated in the load, present only in the currents. However, it should be noted that there is no necessity to separate the residual currents, since they must be fully compensated for, along with all the reactive current and the unbalanced active currents.

(18)$i_u^a=\frac{P_{\mu }}{V_{\mu }^2}{v}_{\mu },$

(19)$i_{\mu }^{ab}=\frac{P}{V_{eq}^2}{v}_{eq},$

(20)$i_{\mu }^{au}=i_{\mu }^a-i_{\mu }^{ab},$

(21)$i_u^r=\frac{W_{\mu }}{{\widehat{V}}_{\mu }^2}{\widehat{v}}_{\mu },$

(22)$i_{\mu }^{rb}=\frac{W}{{\widehat{V}}_{eq}^2}{\widehat{v}}_{eq},$

(23)$i_{\mu }^{ru}=i_{\mu }^r-i_{\mu }^{rb},$

(24)$i_{\mu }^v=i_{\mu }-i_{\mu }^a-i_{\mu }^b.$

Inside an APPF, the current flowing through the inverter will result in losses in the elements of the circuit. Therefore, the losses need to be compensated for by employing the capacitor charging current $i_{\mu }^C$. This current must be balanced and completely in phase with the input voltages, that is, according to (25), it must be proportional to $i_{\mu }^{ab}$, being i_cap the result of the voltage compensator of C_f and $i_{máx}$ a reference value for normalization of $i_{\mu }^{ab}$. Thus, the resulting current to be compensated is expressed in (26).

(25)$i_{\mu }^C=-\frac{i_{cap}\times i_{\mu }^{ab}}{i_{máx}},$

(26)$i_C{}_{\mu }=i_{\mu }^r+i_{\mu }^{au}+i_{\mu }^v+i_{\mu }^C$

4. Programming Architecture

As can be seen in Table 4, the use of logic elements responsible for rearranging the board hardware for the circuit described in VHDL is about 7 times higher for CPT. However, the high capacity of the FPGA board opens the possibility for the implementation of any of the tested theories in addition to more robust controllers.

Registers are not a limitation of the FPGA device once they are built with the board’s logic elements to store data. For the calculus of the CPT and control of the APPF, approximately three times more information was stored when comparing to the IPT strategy.

The pins used are the same for both implementations, as they correspond to the input and output signals. Considering a three-phase system and an APPF fed from the DC capacitance, the number of parallel processes for both theories is the same.

The multiplier elements are the board’s units, extra for the logic elements, and for executing signal multiplication operations efficiently. In this regard, CPT requires about 2.6 times more elements than IPT, occupying almost all the blocks of the board. For both cases, PLL blocks, responsible for adjusting the phase of a signal generated by the code to match an input signal, and memory bits, used for implementations using look-up tables, were not used.

Figure 4 shows a flowchart to illustrate the steps for programming the power theories with the FIL technique. The ADC represents the conversion from the simulator to the board, and the DAC represents the simulator receiving the signals. The calculus are based on the equations of Section 3 and Table 4.

5. Simulation Results

In Figure 5, it is possible to observe the compensation currents for each phase and the neutral of both theories responsible for providing the reference to the APPF.

For the selected loads, it appears that the compensation currents are quite similar. This result demonstrates that for certain cases of compensation, the two theories coincide in their formulation.

For the system operating with FIL, in Figure 6 and Figure 7, respectively, the source currents and the voltage in the APPF capacitance for both theories are observed.

The source currents can be analyzed in three distinct periods. In the first, not considered in this work, the capacitance C_f is charged. In the second, the unbalanced currents and the presence of harmonics are observed. In the third period, both controllers are started and the APPF starts to operate.

As can be seen, as soon as the compensation starts, the CPT presents a greater transient in the currents. This transient is a consequence of the multiple integral calculus and RMS values necessary to calculate the compensation currents. However, after the end of the transitory period, the compensation is as effective as in the IPT, leading the source to feed the system with a power factor (PF) of 0.9988.

Right at the beginning of the APPF operation, there is a relevant behavior to consider. The action of compensation causes sudden changes in the currents, leading to high derivatives that are not instantly absorbed by the circuit. Therefore, a transitory period is necessary until the stabilization of the currents according to the generated references.

As for the capacitance voltage, it is noticed that its dynamics in the CPT are faster than in the IPT even though its crossing-over frequency is higher than in the CPT. This is due to the quantities that are used in the voltage loop in each of the theories. In both theories, the voltage controller receives the difference between the 400 V reference and the capacitor voltage. However, the controller at the IPT sends a power signal that is added to the theory’s calculations and then transformed into current signals. In the CPT, the controller output is already given in a current format and is added directly to the compensation currents. Furthermore, it is observed that due to the voltage transient in the IPT, its current transient is also affected, and it is slower than that noticed in TPC. Additionally, the CPT provided a less oscillatory power as observed in Figure 7.

Because the reached PF is basically unitary, it is evident that the grid currents do not remain with some lag due to the presence of harmonics or uncompensated reactive energy. From Figure 8 and Figure 9, in which, respectively, the active and reactive powers supplied from the grid are presented, it is confirmed that in average terms, the entire reactive portion has been compensated.

By analyzing the Total Harmonic Distortion (THD), it is possible to observe how the harmonics were treated in the system. Table 5 presents the data regarding the THD for the grid phases before and after the insertion of the APPF in the system.

According to the results, one can verify that the THD is considerably reduced compared to the system without APPF correction, resulting in 1.9% and 2.1%, when CPT is in operation, and in less than 1% when IPT is in operation. In Figure 10, the harmonic content up to the fiftieth order of phase “a” is presented for the APPF running with the CPT. This behavior is similar for the remaining phases and for the IPT theory.

It is also important to verify the compensation effectiveness by observing the individual harmonics as shown in Table 6. Table 6 shows the individual harmonics up to the 13th. For higher orders, all verified values are lower than 0.03%. As can be seen, the CPT has a higher harmonic content than the IPT, considering the load scenario in Table 2. However, its harmonic content is distributed among the 3rd, 5th, and 7th harmonics. As in the IPT, this content is relevant until the 13th.

Another behavior that should be highlighted is the greater impact of the third harmonic (180 Hz). For the case analyzed in Figure 10, this harmonic corresponds to about 1.94% of the fundamental. This frequency inserted into the current is associated with the capacitor voltage control. Its power is provided by the operation as a three-phase rectifier, which, in turn, ends up generating current harmonics with triple the fundamental frequency.

Eventually, one can conclude why the harmonics of the CPT and the IPT are slightly different. Basically, it is a direct consequence of the voltage outer loop in each theory. Depending on the tuning, the outer loop dynamic can be somewhat significant on the current and the resulting THD.

In order to compare the compensation effectiveness of the present work, we have chosen two works from the current literature. The work in [29] shows the effectiveness of an APPF regarding current compensation using a Genetic Algorithm and a Queen-Bee assisted Genetic Algorithm to optimize the controller coefficients. In [30], the current control is performed through a model predictive control. The strategy has as its purpose balance between THD, to maintain its level below IEEE standards and the value of the switching frequency. Therefore, they used a variable switching frequency around the base value shown in Table 7.

It is worth mentioning that in both works, resistances and inductances are used in the power source and at the point of connection of the loads, representing the cables impedance. Another important fact is the usage of an initial voltage in the DC bus capacitor. In [29] it is assumed as 200 V, whereas in [30], it is assumed as 100 V. In both cases, these assumptions facilitate the compensation of the APPF reducing the current peaks and settling time. Regarding the impedance, it helps the compensation currents to flow exclusively to the load. However, it is important to emphasize that in this work, the used initial capacitor voltage nor additional impedances are used.

For the comparison scenario, the grid and the power electronics converter were the same, but the loads were changed to comply with the aforementioned references. A full-wave rectifier feeds the RL loads, and these data are shown in Table 7. Figure 11 and Figure 12 show the current and voltage waveforms at the power source for both load situations of [29,30]. Table 8 compares the THD of the current for each phase with the two mentioned controls.

Furthermore, the results of the settling time for each case are also analyzed. Observing the work of [29], the obtained settling time was 0.23 s and for [30], there is no available data.

Regarding the application of the PI controllers in IPT and CPT, ignoring the charging time of the capacitor, which is negligible, and knowing that the control starts to operate after two grid cycles, in t = 0.033 s, the settling time for IPT with loads of [29,30] are, respectively, t = 0.17 s and t = 0.10 s. As for the CPT, they are t = 0.12 s and t = 0.10 s. The steady-state regime was considered when the values were within $\pm 2\%$.

6. Conclusions

The operation of parallel processes and the high processing speed of the FPGA are significant differentials for implementing APPF with a high switching frequency. Furthermore, the usage of the simulator and the FPGA board establishing the FIL operation to validate the control and the necessary calculations proved to be a powerful prototyping tool. Such technology allowed for the comparison between the two compensation strategies, with different methods for the reference currents generation with embedded controllers without the necessity for the physical topology for validations and without changing hardware for digital implementation.

Both theories proved valid for the APPF operation, hardware synthesis, and FPGA-in-the-loop implementation. However, since the CPT presents a more complex calculus with more processes than the IPT, a great processing requirement was identified in the usage of logic elements and blocks dedicated to the multiplication on the FPGA board. As a result, the implementation of each theory must be evaluated given the needs of the project and the available computational resources. If the compensation necessity is only related to the reactive power and the available resources are of worry one may use the IPT. If the computational resource is not an important point and different portions of power are necessary to be known or compensated, the CPT is the ideal theory to be implemented.

It is noteworthy that the FIL validation technique opens doors for comparing the performance of different linear and non-linear controllers for the implementation of APPF. In addition, other topologies and control techniques for active power filters can be analyzed to reduce the consequences of their insertion into the system through the FIL implementation. Finally, it is important to verify the quality of the achieved compensation with very low remaining distortion using the FPGA in comparison to other proposals. This is related to the high switching frequency of the used APPF allowed by the high processing power of the FPGA board.

Author Contributions

Conceptualization and methodology, N.D.d.A. and R.B.G.; validation, N.D.d.A., R.B.G. and R.L.R.S.; formal analysis, R.B.G., E.A.B. and M.A.G.d.B.; investigation, N.D.d.A. and R.L.R.S.; resources, N.D.d.A., M.A.G.d.B. and R.L.R.S.; writing—original draft preparation, N.D.d.A.; writing—review and editing, M.A.G.d.B. and E.A.B.; supervision, R.B.G.; project administration, R.B.G.; funding acquisition, E.A.B. All authors have read and agreed to the published version of the manuscript.

Institutional Review Board Statement

Not applicable.

Informed Consent Statement

Not applicable.

Data Availability Statement

Not applicable.

Acknowledgments

The authors want to thank the Federal University of Mato Grosso do Sul—UFMS.

Conflicts of Interest

The authors declare no conflict of interest.

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Figures and Tables

Figure 1. FIL scheme for the four-wire APPF simulation.

Figure 2. IPT control loops.

Figure 3. CPT control loops.

Figure 4. Flowchart to implementing FIL with IPT and CPT theories.

Figure 5. Power theory compensated currents obtained by FIL.

Figure 6. Comparison of the grid currents through FIL for the power theories. Phases (a), (b), (c) and neutral are in blue, red, yellow, and purple, respectively.

Figure 7. Comparison of Cf voltage using FIL for the power theories.

Figure 8. Grid supplied active power with APPF operating.

Figure 9. Grid supplied reactive power with APPF operating.

Figure 10. Phase “a” total harmonic distortion with APPF.

Figure 11. Comparison between CPT and IPT for the loads used in [29].

Figure 12. Comparison between CPT and IPT for the loads used in [30].

Table 1

Control parameters and system components.

Parameters	Values
Switching frequency—fs	400 kHz
Filter inductance—Lf_μ	62.5 μH
DC bus capacitance—Cf	1.8 mF
Filter resistance—Rf	2.4 mΩ
DC bus voltage—VCC	400 V
Electrical system line voltage—VLRMS	220 V
Maximum current ripple—Δimáx	2 A

Table 2

Loads supplied by the system.

Loads	Phase a	Phase b	Phase c
Linear—RL	1 kW; 0.1 kVAr	0.9 kW; 0.09 kVAr	0.5 kW; 0.11 kVAR
Rectifier—RL	10 mH; 40 Ω	10 mH; 40 Ω	10 mH; 40 Ω
Linear—R	80 Ω	80 Ω	-

Table 3

Gains of analog (K) and digital (g) controllers.

Parameters	Ci(s); Ci(z) (IPT)	Cv(s); Cv(z) (IPT)	Ci(s); Ci(z) (CPT)	Cv(s); Cv(z) (CPT)
Kp	0.4257	750.7	0.4257	57.88
Ki	5.35 × 104	6.132 × 105	5.35 × 104	3637
g x1	0.42574634733	750.676024414	0.42574634733	57.879697639
g x2	−0.3722454834	−750.062866166	−0.3722454834	−57.876060950

Table 4

Computational resources need for each theory.

Implemented Power Theory	IPT	CPT
Logical elements	7.839/114.480 (7%)	54.833/114.480 (48%)
Registers	463	1377
IOs	483/529 (91%)	483/529 (91%)
Memory bits	0/3.981.312 (0%)	0/3.981.312 (0%)
9 bits embedded multipliers	180/532 (34%)	461/532 (87%)
PLLs	0/4 (0%)	0/4 (0%)

Table 5

System total harmonic distortion.

THD	Phase a	Phase b	Phase c
Without APPF	10.79%	11.24%	17.72%
APPF—CPT	1.95%	2.05%	1.99%
APPF—IPT	0.80%	0.81%	0.81%

Table 6

Individual harmonics up to the 13th.

		CPT			IPT
Order	Frequency	Phase a	Phase b	Phase c	Phase a	Phase b	Phase c
2nd	120	0.02	0.03	0.03	0.21	0.39	0.40
3rd	180	1.95	1.99	1.96	0.82	0.74	0.86
4th	240	0.00	0.01	0.01	0.05	0.16	0.16
5th	300	0.14	0.15	0.14	0.12	0.16	0.24
6th	360	0.00	0.01	0.01	0.02	0.09	0.09
7th	420	0.14	0.14	0.14	0.12	0.15	0.18
8th	480	0.01	0.01	0.02	0.02	0.06	0.06
9th	540	0.00	0.00	0.00	0.01	0.06	0.06
10th	600	0.00	0.01	0.01	0.01	0.05	0.05
11th	660	0.02	0.02	0.02	0.06	0.09	0.05
12th	720	0.00	0.00	0.00	0.01	0.05	0.05
13th	780	0.01	0.01	0.01	0.05	0.08	0.05

Table 7

Load parameters for comparison purposes.

Parameters	[29]	[30]
Loads	LL = 40 mH; RL = 50 Ω	LL = 160 mH; RL = 28 Ω
Grid frequency and voltage	fg = 50 Hz; Vg = 140 V	fg = 50 Hz; Vg = 100 V
DC link	Cf = 3300 µF; VDC = 300 V	Cf = 100 µF; VDC = 200V
Switching frequency	fs = 15 kHz (base)	fs = 20 kHz

Table 8

THD of the supply current in %.

		Phase a		Phase b		Phase c
Control/Power Theory	Workbench	Without APPF	With APPF	Without APPF	With APPF	Without APPF	With APPF
PI/IPT (Load [29])	FIL	29.45	0.70	29.45	1.06	29.45	0.96
PI/CPT (Load [29])	FIL	29.45	0.28	29.45	0.27	29.45	0.28
PI/IPT (Load [30])	FIL	34.20	0.45	34.20	0.51	34.20	0.58
PI/CPT (Load [30])	FIL	34.20	0.25	34.20	0.25	34.20	0.25
GA [29]	Simulation	22.63	3.15	22.63	3.15	22.63	3.15
GA [29]	Hardware	22.63	3.71	22.63	3.94	22.63	3.18
QBGA [29]	Simulation	22.63	1.96	22.63	1.96	22.63	1.96
QBGA [29]	Hardware	22.63	3.50	22.63	3.12	22.63	3.01
MPC [30]	Simulation	28.47		3.53 1∅
MPC [30]	Hardware	24.90		3.70 1∅

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