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The complexity of VLSI designs has grown to the extent that there are substantial doubts about the designers' ability to keep up with process capabilities. This premise has given rise to the so called, silicon design crisis. The development of more sophisticated design synthesis tools, is, therefore, of paramount importance if this crisis is to be averted, and the full potential of modern VLSI fabrication techniques is to be exploited.
This research investigates a prototype hardware synthesis system, which transforms a high level (algorithmic) behavioural description into a lower level (functional block) structural one. The behavioural specification consists of a number of sequential occam processes which are active concurrently, and thus communicate via channels. Each sequential process is transformed into a single control data path pair machine, which communicates with its neighbours using direct physical connections. The structural description is expressed in ELLA. Synthesis is accomplished in three stages.
During the first stage, which utilises a rule-based approach, each sequential occam process definition is translated into separate control and data path sections.
The second stage, uses a compiler, ASMELL, to automatically convert the intermediary, ASM-based, control path description into a tailored version of a general finite state machine, described in ELLA. This new control path representation, and the synthesised data path description are compiled into an EASE context, where they are combined into a single ELLA function.
The final stage of synthesis, imports/exports these combined ELLA functions between EASE contexts to permit a complete structural description to be assembled.
With the exception of the ASMELL compiler portion, all the synthesis steps are, at present, accomplished manually. However, the results obtained are encouraging, and automation of the system would seem to be worth investigating. Two complete example translations are provided.