A 7–13 GHz 10 W High-Efficiency MMIC Power Amplifier in 0.25 µm GaN HEMT Process

Abstract

With the increase in applications of the millimeter wave spectrum for phased array radar systems, mobile 7–13 communication systems, and satellite systems, the demand for a wideband, high-efficiency, high-power monolithic microwave integrated circuit (MMIC) power amplifier (PA) is increasing. In this paper, a 7–13 GHz 10 W high-efficiency MMIC PA is designed. This amplifier consists of a two-stage circuit structure with two high electron mobility transistor (HEMT) cells for the driver stage and four HEMT cells for the power stage. To ensure high efficiency and a certain output power ($P_{out}$), both the driver–stage and power–stage transistors use a deep Class–AB bias. At the same time, in order to further improve the efficiency, low-loss and second–harmonic tuning techniques are used in the output and inter-stage matching networks, respectively. Finally, the electromagnetic simulation results show that within a frequency of 7–13 GHz, the amplifier achieves an average saturated continuous wave (CW) $P_{out}$ of 40 dBm, a small signal gain of 14.5–15.5 dB, a power-added efficiency (PAE) of 30–46%, and the input and output return loss are better than 5 dB and 8 dB, respectively.

1. Introduction

In recent years, with the rapid development of equipment represented by synthetic aperture radar (SARs), a large number of transmit–receive (T/R) components have put forward higher requirements on the power, integration, bandwidths, and efficiency of the amplifier [1,2,3,4,5,6]. To meet the above requirements, the monolithic microwave integrated circuit (MMIC) MMIC is the preferred choice for such power amplifiers [7,8,9]. In order to achieve a higher power level, a popular approach is to combine the output power ($P_{out}$) of several individual power amplifier (PA) chips; however, this combination can cause an increased loss and degraded power efficiency in the synthetic network due to the increased number of PA chips [10,11,12]. Therefore, to reduce the loss and simplify the system structure, a high-power MMIC PA is very much desired [13].

For the development of a high-power MMIC PA, the gallium nitride (GaN) process is well-suited due to its characteristics of a higher breakdown voltage, a higher $P_{out}$, wideband capability, and high efficiency [14,15,16,17,18,19]. Given these advantages, various developments in high-power GaN MMIC PAs have been reported to cover the frequency range of the X band [2,20,21,22,23,24,25,26,27]. A 7.8–8.8 GHz two-stage high-efficiency MMIC PA based on a harmonic tuning structure was developed in [2] to achieve better than the 20 W of out power associated with a power-added efficiency (PAE) of above 50%. In [21], an 8–12 GHz compact MMIC PA was presented to deliver an $P_{out}$ from 47.5 dBm to 48.7 dBm and a PAE from 40% to 45%. In [22], an 8.8–10.4 GHz GaN PA was implemented to deliver an out power of 30 W with a relatively low PAE of 38%. Nevertheless, the PA exhibits a relatively large chip size. In [27], a high–power single-chip X-band Class-F power amplifier was reported.. The fabricated Class-F PA delivered a bandwidth of 1.6 GHz at the point of 50% PAE, and a high power density of 4.42 W/mm was demonstrated. In conclusion, almost all of these results were achieved in a narrow frequency band. Therefore, achieving a high PAE while maintaining relatively high power in a wide bandwidth remains a design challenge.

In this paper, a design procedure for a 7–13 GHz GaN MMIC PA is presented in detail, and the MMIC PA is designed in 0.25 µm gate length GaN high electron mobility transistor (HEMT) technology. The remaining part of this paper is organized as follows: Section 2 presents the utilized GaN HEMT process. Section 3 shows the detailed design procedures of the proposed PA, the design of the driver and power stages of the MMIC PA, and the design of the impedance matching networks. In Section 4, the experimental results are presented, and a conclusion is given in Section 5.

2. The 0.25 μm GaN/SiCProcess

GaN process is particularly suitable for the implementation of a high-efficiency MMIC PA due to the characteristics of high power, wideband capability, high performance, and high efficiency. In this paper, a GaN/SiC HEMT process with 0.25 µm gate length on a 100–µm–thick of SiC substrates is utilized for implementation of this PA. In this process, the maximum drain biases rating of 40 volts. Cutoff frequency ($f_t$) and maximum frequency ($f_{max}$) of the transistors are 25 and 75 GHz, respectively. This process utilizes a source–coupled field–plate design to provide the breakdown voltage required for reliable operation at a high drain bias. This process offers two interconnected metal layers, high–reliability metal–insulator–metal (MIM) capacitors with 215 pF/mm² density, and precision tantalum nitride (TaN) resistors with 50 Ω/square sheet, resistivity. This process provides integrated source via (ISV) transistor device model, the structure features good electrical ground from front to backside. This process also provides air bridge, back–vias and MIM capacitors with back–vias. According to the handbook of the process, the 0.25 µm gate length GaN HEMT is well-suited for high–power applications from the C–band to the Ku–band and exhibits a high degree of process maturity [8].

3. Circuit Design

3.1. Power Amplifier Structure

The goals for this design include a 7–13 GHz bandwidth, an output power gain of 14 dB, an average $P_{out}$ of 40 dBm, and a PAE of better than 30%. The main specifications for the amplifier are summarized in Table 1.

According to Table 1, a minimum power gain of 14 dB is among the design goals of the MMIC PA. Since the maximum available gain of the chosen transistors is about 10 dB at 13 GHz, and assuming a total loss of 6 dB for the matching networks, at least two amplification stages are required.

The primary task of the power-stage transistors is to deliver the required $P_{out}$. According to load–pull simulations biased at $V_{gs}$= −2 V and $V_{ds}$= 28 V, the power density of the used transistors is about 5.6 W/mm gate width. To achieve a 40 dBm $P_{out}$, a total transistor width of 2 mm is required. Trading off the number of fingers and the finger width, a total amount of 16 fingers is chosen and arranged as four 4 × 125 μm transistors. Figure 1a,b show the I–V curve and transfer curve (at $V_{gs}$= −2 V and $V_{ds}$ = 28 V) of the 4 × 125 μm device, respectively.

Moreover, the driver stage needs to provide enough linear $P_{out}$ so that the power stage can reach saturation. Simultaneously, it is also necessary to minimize the power consumption on the HEMT of the driver stage in the design to improve the overall output efficiency of the developed PA. Taking the above into consideration, we adopt two HEMT cells with a total gate width of 1 mm (2 × 4 × 125 µm GaN HEMT) for the driver stage. Moreover, the driving ratio of the multistage wideband amplifier is about 1:2, which can ensure good inter-stage matching (IMN) and broadband performance and avoid the complexity or the asymmetry in the ratios of 1:4 or 1:8 [13]. Figure 2 shows the block diagram of the proposed MMIC PA.

3.2. Stability Analysis and Design

The stability analysis is an essential step in this MMIC PA design. To ensure the stability of the developed MMIC PA, stability circuits were designed for each HEMT. Figure 3 shows the block diagram of the designed stability circuits. A parallel RC network, which is composed of the parallel connection of a resistance and a capacitance, is inserted at the gate of the GaN HEMT. Figure 4a,b give the simulation results of the maximum gain and stability factor, respectively. It can be seen that the simulated stability factors are higher than 1.03 throughout a frequency from 0 to 20 GHz, which confirms that the designed stability circuit can effectively improve the stability.

3.3. Broadband Design Consideration

The design of a high-efficiency power amplifier requires obtaining the optimal impedance region within the target frequency band. In this paper, we adopt the method of a load–pull simulation to obtain the optimal impedance. Table 2 gives the load–pull simulation result of the two parallel HEMTs with stability circuits for the power stage of the developed MMIC PA. These optimum impedance points are selected based on tradeoffs among the PAE, $P_{out}$, and bandwidth. It is also observed that the optimal load impedance of the device is not constant for the whole frequency. Within the frequency range of 7–13 GHz, the $P_{out}$ and PAE are better than 37 dBm and 54%, respectively. Figure 5 gives the load–pull contours of the $P_{out}$, PAE, and ideal load impedance at 7 and 13 GHz.

To ensure a high-frequency performance of this PA, thereby improving the gain flatness, the optimal load $Z_{opt}$ is chosen to be 12 GHz. Figure 6 gives the simulation result of the $P_{out}$ and PAE versus the input power ($P_{in}$) at 12 GHz for a 2 × 4 × 125 µm GaN HEMT with an optimal load impedance under CW conditions. It can be seen that as the $P_{in}$ increases, the $P_{out}$ gradually increases. The peak value of the PAE appears around $P_{in}$= 27 dBm, at the same time, the $P_{out}$ also reaches a relatively high power level.

3.4. Design of Output Matching Network (OMN)

The design of the OMN needs to comprehensively consider the following five aspects [13]:

• (1). Achieve conjugate matching and attain the maximum PAE while maintaining a relatively high power;

• (2). The power transmitted by the microstrip line and the components cannot exceed its power tolerance;

• (3). Network matching should be as simple as possible to reduce losses;

• (4). The standing wave coefficient of the output terminal should not be too large, which is convenient for interconnection with external systems;

• (5). The design of the DC feeding network is reasonable.

A low-loss OMN circuit is very important for gaining a high PAE [8]. To minimize the insertion loss, the OMN circuit consists of a low-loss double-layer microstrip and a high-reliability MIM capacitor. The final topology of the proposed OMN is shown in Figure 7.

The structure of the OMN is simple; the insertion loss is reduced as much as possible on the premise of satisfying conjugate matching. The insertion loss and return loss of the OMN are shown in Figure 8a. It is seen that the loss of the output matching circuit is 1.3–0.6 dB across the frequency range of 7–13 GHz, with a return loss of better than 12 dB, which means the developed amplifier has a high efficiency and high $P_{out}$ performance. Figure 8b demonstrates the matching effect reflected by the output matching network. It can be seen that the points of actual load impedance are basically located in the optimum impedance region throughout a frequency from 7 to 13 GHz, that mean a good output matching is achieved.

3.5. Design of Inter-Stage and Input Matching Network

There are usually two ways to design an IMN. Method 1 is by transforming Impedance A to 50 Ω and then transforming it from 50 Ω to Impedance B, and Method 2 is transforming Impedance A to Impedance B directly, as shown in Figure 9a and Figure 9b, respectively.

The advantage of Method 1 is that both Impedances A and B can be considered to be transformed from the 50 Ω standard impedance, which is relatively stable and reduces the influence of the optimal source/load impedance change caused by the change in the working state of the HEMT on the matching accuracy; the disadvantage is that the matching network will become complex, thereby increasing the chip area. The advantages of Method 2 are that Impedances A and B are directly transformed from each other, the matching network is simple, and the chip area is saved; however, the difficulty of the matching network design will also increase. After, comprehensive consideration, this design adopts Method 2 to design the IMN. Simultaneously, in order to improve the efficiency, the second-harmonic control network is used in the IMN, which is composed of an inductor and a capacitor in series. The circuit structure of the IMN is shown in Figure 10a. It can be observed that the structure of the matching network between the two stages is simple and occupies a small chip area. The design of the IMN takes into account the same factors as the design of the OMN. Figure 10b presents the structure of the proposed IMN.

The insertion loss and return loss simulation results of the ISMN are shown in Figure 11a. With a return loss better than 12 dB, the insertion loss is 1.4–0.7 dB across the frequency range of 7–13 GHz; the simulation result of the IMN is shown in Figure 11b. With a return loss better than 10 dB, the insertion loss is 2.8–1.2 dB across the frequency range of 7–13 GHz.

4. Power Amplifier Measurement Results

This two-stage GaN MMIC PA is implemented in a 0.25 μm gate length GaN/SiC HEMT process. Figure 12 demonstrates the final layout of the designed MMIC PA. Including the testing pads, the design occupies a size of 4.5 × 2.6 mm².

In order to verify this design, the developed GaN PA adopts a Class-AB bias point with a drain voltage of 28 V, a gate voltage of −2 V, and a total gate current of 954 mA. The electromagnetic simulated(EM) S-parameters of the layout are shown in Figure 13a. It can be seen that in the frequency range of 7–13 GHz, the amplifier achieves a small signal gain of 14.5–15.5 dB with a gain flatness of less than ±1 dB, and the input and output return loss are better than 5 dB and 8 dB, respectively. Moreover, the simulated PAE and $P_{out}$ results of the large signal are illustrated in Figure 13b. The designed MMIC PA achieves a PAE of 30–46% with an $P_{out}$ of 40 dBm over the entire 7–13 GHz bandwidth.

In order to evaluate this MMIC PA, the performance comparison with the previously reported GaN PAs is presented in Table 3. It is obvious that the proposed PA exhibits quite a superior performance, including a high efficiency, high $P_{out}$, and wide bandwidth in the MMIC power amplifiers.

5. Conclusions

In this paper, a 7–13 GHz high-efficiency MMIC PA design methodology and its experimental results have been presented. The designed amplifier, with a compact chip area of 4.5 × 2.6 mm², attains an average $P_{out}$ of 40 dBm, an average power gain of 14 dB, and a PAE of 30–46%, and the input and output return losses are better than 5 dB and 8 dB, respectively, over the entire 7–13 GHz bandwidth.

Author Contributions

Data curation, A.H. and T.L.; Investigation, A.H. and T.L.; Methodology, A.H., Y.L., X.Q., T.L. and Y.P.; Project administration, Y.L. and X.Q.; Resources, Y.L. and X.Q.; Software, A.H.; Writing—original draft, A.H.; Writing—review and editing, A.H., Y.L., X.Q., T.L. and Y.P. All authors have read and agreed to the published version of the manuscript.

Institutional Review Board Statement

Not applicable.

Informed Consent Statement

Not applicable.

Data Availability Statement

The data may be obtained from the authors upon request.

Conflicts of Interest

The authors declare no conflict of interest.

Publisher’s Note: MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Figures and Tables

Figure 1. The characteristics of 0.25 μm GaN HEMT: (a) I–V curve of 0.25 μm GaN HEMT; (b) transfer curve of 0.25 μm GaN HEMT.

Figure 2. The circuit structure block diagram of the 7–13 GHz MMIC PA design.

Figure 3. Block diagram of the stability circuits.

Figure 4. Simulated results of stability circuits: (a) maximum gain; (b) stability factor.

Figure 5. Load–pull contours for [Forumla omitted. See PDF.] and PAE from 7 to 13 GHz and ideal load impedance.

Figure 6. [Forumla omitted. See PDF.] and PAE of 2 × 4 × 125 µm HEMT under frequency of 12 GHz.

Figure 7. Circuit structure of the proposed OMN.

Figure 8. Simulation result of the OMN: (a) insertion loss and return loss; (b) points of actual load impedance.

Figure 9. Impedance transform diagram: (a) indirect change; (b) direct change.

Figure 10. The block diagram of the circuit structure: (a) ISMN; (b) IMN.

Figure 11. Return loss and insertion loss of the (a) ISMN; (b) IMN.

Figure 12. Schematic diagram of the MMIC PA layout.

Figure 13. Layout simulation results: (a) results for small signal; (b) results for large signal.

Table 1

Requirements for 7–13 GHz MMIC PA.

Parameter	$\mathit{S}\mathit{p}\mathit{e}\mathit{c}\mathit{i}\mathit{f}\mathit{i}\mathit{c}\mathit{a}\mathit{t}\mathit{i}\mathit{o}\mathit{n}$	Unit
Frequency range	7–13	GHz
Average $P_{out}$	40 (10)	dBm (W)
PAE	30	%
Power gain	14	dB

Table 2

Load–pull simulation result of two parallel HEMTs.

Frequency (GHz)	${\mathit{Z}}_{\mathit{o}\mathit{p}\mathit{t}}$	${\mathit{P}}_{\mathit{o}\mathit{u}\mathit{t}}$ (dBm)	PAE (%)
7	8.25 + j18.69	39.8	59.63
8	17.59 + j31.16	37.52	57.51
9	6.03 + j16.04	38.65	57.24
10	11.51 + j22.2	37.37	57.68
11	3.95 + j13.23	38.37	56.59
12	4.26 + j11.85	37.57	55.42
13	9.29 + j20.16	37.51	54.68

Table 3

Comparison to previously published MMIC PAs.

Ref.	Process	Frequency (GHz)	$\mathit{P}\mathit{o}\mathit{w}\mathit{e}\mathit{r} \mathit{g}\mathit{a}\mathit{i}\mathit{n}$ (dB)	${\mathit{P}}_{\mathit{o}\mathit{u}\mathit{t}}$ (dBm)	PAE (%)
[1]	GaN	6–18	11	39.2	24.5
[2]	GaN	7.8–8.8	20	43	50
[21]	GaN	8–12	20	47.5–48.7	40–45
[22]	GaN	8.8–10.4	17	45–46	38–44
[28]	GaAs	7.5–12.5	17.5	39	30–40
This work	GaN	7–13	14	40	30–36%

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