MOSFET Physics-Based Compact Model Mass-Produced: An Artificial Neural Network Approach

Abstract

The continued scaling-down of nanoscale semiconductor devices has made it very challenging to obtain analytic surface potential solutions from complex equations in physics, which is the fundamental purpose of the MOSFET compact model. In this work, we proposed a general framework to automatically derive analytical solutions for surface potential in MOSFET, by leveraging the universal approximation power of deep neural networks. Our framework incorporated a physical-relation-neural-network (PRNN) to learn side-by-side from a general-purpose numerical simulator in handling complex equations of mathematical physics, and then instilled the “knowledge’’ from the simulation data into the neural network, so as to generate an accurate closed-form mapping between device parameters and surface potential. Inherently, the surface potential was able to reflect the numerical solution of a two-dimensional (2D) Poisson equation, surpassing the limits of traditional 1D Poisson equation solutions, thus better illustrating the physical characteristics of scaling devices. We obtained promising results in inferring the analytic surface potential of MOSFET, and in applying the derived potential function to the building of 130 nm MOSFET compact models and circuit simulation. Such an efficient framework with accurate prediction of device performances demonstrates its potential in device optimization and circuit design.

1. Introduction

Compact models work as a bridge between the fabrication process and circuit design. They are designed to accurately reproduce minute details of device electrical characteristics, which are essential in the design of digital, analog, mixed-signal, and RF-integrated circuits. This requires the model to be accomplished in a manner consistent with the device operation physics, and with a model structure that remains invariant of fabrication process particulars. Several types of compact model for a Mental-Oxide-Silicon Field-Effect transistor (MOSFET) have been developed, including the threshold-voltage(${\mathrm{V}}_{\mathrm{th}}$)-based compact model, the inversion-charge(${\mathrm{q}}_{\mathrm{i}}$)-based compact model, and the surface-potential(${\mathsf{\varphi }}_{\mathrm{s}}$)-based compact model. Among these compact models, the ${\mathsf{\varphi }}_{\mathrm{s}}$-based compact model has achieved widespread success and is most frequently used in modern circuit simulators for its accurate description of major physical effects, which are responsible for the characteristics of scaled MOSFETs. The expression formulation of ${\mathsf{\varphi }}_{\mathrm{s}}$ is the key component of ${\mathsf{\varphi }}_{\mathrm{s}}$-based compact models, and needs to be carefully designed in solving implicit transcendental equations. Aggressive down-scaling of the device and the resultant physical effects have made it very challenging to obtain analytic solutions from complex equations in mathematical physics [1,2]. On the other hand, though numerical solvers [3] can be high-quality alternatives, the non-differentiable solution is unfit for circuit simulation or design optimization; furthermore, a solver may take hours just to solve the equation for a single condition, being computationally intractable even if it can be applied on demand.

Can we free ourselves from challenging theoretic effort and maximally automate the process of building an analytic device surface potential expression that can be applied efficiently in system simulation, design, and optimization? The strength of an artificial neural network (ANN) is considered as one of the effective ways by which to achieve the goal. An ANN endeavors to recognize underlying relationships in a set of data through a process that mimics the way the human brain operates and can adapt to changing input, so the network generates the best possible result without needing to redesign the output criteria. An ANN consists of an input layer of neurons taking the input data, one or two hidden layers of neurons processing the input data, and a final layer of output neurons sending the predicted output, which is compared with the actual output. Based on the error, the parameters (weight and bias) in an ANN are changed and are then fed into the network again to improve the accuracy of prediction. Compared to other machine learning algorithms, an ANN has the ability to learn and adapt to unknown systems, and can fully approximate any complex nonlinear relationship, giving analytical expression of the input and output data, which is essential in the compact model development.

Several studies have been conducted to apply artificial neural networks in building models for MOSFET. In the literature [4,5], the electrical characteristics of MOSFET, including I-V curves and C-V curves, were directly adopted as the training data of the ANN. Two hidden layers were involved in the network and the learning result is achieved. However, with little consideration of the physics of the device’s working principle, the modeling variation is complex in the pure-deep-learning-based model, which is important in device design and optimization. In [6], a deep-learning-assisted MOSFET I-V compact modeling method was proposed. In the method, the ANN acts as a correction term to the traditional BSIM compact model, which increases the compatibility of the classical model with advanced node devices. This method presents a possible prospect for the development of future compact models. However, the direct correction to the I-V curve by the ANN also conceals the important physical information in advanced MOSFETs, which is the optimization and development of scaling devices.

In this work, we propose an innovative artificial neural network (ANN) [7] to obtain the surface potential for compact modeling, and thus, preserve physical information in the subsequent process of building the compact model. The key idea is to use a dedicated numerical simulator [8] (e.g., TCAD) as a “teacher”, and feed its output across highly diverse device data to the “student”, a so-called physical-relation-neural-network (PRNN). The PRNN is a universal approximator that combines general-purpose data fitting with domain-specific physical relations. Therefore, it can effectively mimic the behavior of the teacher, and instill the learned “knowledge” from the solver into the neural network, effectively closing the gap between discrete, numerical simulations and continuous, analytic modeling. We demonstrate the impressive results of our approach in obtaining accurate, analytic surface potential in 130 nm MOS devices. It only requires a simple substitution to generalize to the new parameters of the device, and human intervention involved in different devices/equations [9] is also expected to be minimal. Our framework will be particularly useful in device simulation acceleration, speeding up and coupling the development of micro-device physics-based compact models and device design optimization.

2. Method Framework

The global picture of the proposed framework is shown in Figure 1. First, TCAD [8] software is used to perform the simulation and generate the training data. The data are fed into a physical-relation-neural-network (PRNN), which is composed of both a physical-relation layer to account for basic, low-level physical prior knowledge, and general-purpose fully-connected layers to further capture data nonlinearity. After training and network optimization, the resultant analytic surface potential is further applied to building 130 nm MOSFET semi-classical compact models (e.g., I-V/C-V characteristics) and circuit simulation.

2.1. TCAD Simulation

The 130 nm node MOSFET is stimulated with the Sentaurus Device TCAD tool, as shown in Figure 2. The simulated training data have two parts: preselected device data/parameter $x_{\mathrm{i}}^{\prime }\mathrm{s}$ (i for sample index), and corresponding surface potential [10] value ${\mathrm{y}}_{\mathrm{i}}^{\prime }\mathrm{s}$ computed by TCAD. Each $x_{\mathrm{i}}^{\prime }\mathrm{s}$ is a d-dimensional vector specifying: the thickness of the gate insulation layer (${\mathrm{T}}_{\mathrm{ox}}$), the gate to source voltage (${\mathrm{V}}_{\mathrm{gs}}$), the drain to source voltage (${\mathrm{V}}_{\mathrm{ds}}$), the length of the channel region (${\mathrm{L}}_{\mathrm{g}}$), the temperature ($\mathrm{T}$), the doping concentration in the channel region (${\mathrm{N}}_{\mathrm{d}}$), and channel locations (x) (Table 1 for details). The $x_{\mathrm{i}}^{\prime }\mathrm{s}$ should cover a diverse range of device/operation conditions to generate a rich training dataset. The simulated potential value ${\mathrm{y}}_{\mathrm{i}}$ is the difference between substrate electrostatic potential and electrostatic potential (one nanometer below the channel surface) [11].

2.2. Physical-Relationship (PR) Layer

The PR-Layer groups the variables in each $x_{\mathrm{i}}$ and applies group-wise transform to account for the desired interaction between parameters; the details are shown in Equation (1), which reflect useful prior knowledge on some simple but fundamental relations of physics [12]. From a learning perspective, incorporating justified variable interactions can effectively reduce sample complexity; i.e., the amount of data needed for training an accurate model [13,14].

(1)${\mathsf{v}}_{\mathrm{i}}{=[\mathrm{V}}_{\mathrm{gs}}{,\mathrm{V}}_{\mathrm{ds}}{,\mathrm{N}}_{\mathrm{d}}{, \mathrm{T}, \mathrm{x}, \mathrm{e}}^{\mathsf{\lambda }\frac{\mathrm{x}-\mathrm{L}}{{\mathrm{t}}_{\mathrm{si}}}}{,\mathrm{e}}^{\mathsf{\lambda }\frac{-\mathrm{x}}{{\mathrm{t}}_{\mathrm{si}}}}{,\mathrm{V}}_{\mathrm{ds}}{\mathrm{e}}^{\mathsf{\lambda }\frac{-\mathrm{L}}{{\mathrm{t}}_{\mathrm{si}}}}{,\mathrm{V}}_{\mathrm{bi}}(1-{\mathrm{e}}^{\mathsf{\lambda }\frac{-\mathrm{L}}{{\mathrm{t}}_{\mathrm{si}}}}{),\mathrm{V}}_{\mathrm{gs}}^2{,\mathrm{V}}_{\mathrm{gs}}-{\mathrm{V}}_{\mathrm{ds}},\log (\frac{{\mathrm{L}}_{\mathrm{Di}}{\mathrm{V}}_{\mathrm{gs}}}{{\mathrm{t}}_{\mathrm{si}}}\left)\right].$

Here,${\mathsf{v}}_{\mathrm{i}}\in {ℝ}^{12\times 1}$, $\mathsf{\lambda }=\sqrt{\frac{{\mathsf{\epsilon }}_{\mathrm{ox}}{\mathrm{t}}_{\mathrm{si}}}{{\mathrm{T}}_{\mathrm{ox}}{\mathsf{\epsilon }}_{\mathrm{si}}}}$, ${\mathrm{L}}_{\mathrm{Di}}=\sqrt{\frac{{\mathsf{\epsilon }}_{\mathrm{si}}{\mathrm{v}}_{\mathrm{t}}}{{\mathrm{qn}}_{\mathrm{i}}}}$ is the intrinsic Debye length, ${\mathrm{V}}_{\mathrm{b}}{=\mathrm{v}}_{\mathrm{t}}\ln (\frac{{\mathrm{N}}_{\mathrm{sd}}{\mathrm{N}}_{\mathrm{d}}}{{\mathrm{n}}_{\mathrm{i}}^2})$ is the build-in potential at the source/drain terminal. Min-Max normalization is then adopted to standardize the data ${\mathsf{v}}_{\mathrm{i}}$ [15].

2.3. Fully-Connected (FC) Layer

In FC-Layers, all neurons in one layer will be fully connected to all neurons in the next layer. These are general-purpose network components, and serve as a nice complement to the PR-Layer in capturing complex nonlinear relations [16] between the device data and surface potential. As shown in Figure 1, we cascade two FC-layers right after the PR-layer, with 64 and 32 neurons, respectively, each activated by the sigmoid function. The two FC-layers are as follows [17].

(2)${\mathsf{h}}_{\mathrm{i}}^1=\mathsf{\sigma }\left({\mathrm{W}}_1^{\mathrm{T}}·{ \mathsf{v}}_{\mathrm{i}}{+\mathsf{b}}_1\right),$

(3)${\mathsf{h}}_{\mathrm{i}}^2=\mathsf{\sigma }\left({\mathrm{W}}_2^{\mathrm{T}}·{ \mathsf{h}}_{\mathrm{i}}^1{+\mathsf{b}}_2\right).$

Here, $h_{\mathrm{i}}^1\in {ℝ}^{64\times 1}, h_{\mathrm{i}}^2\in {ℝ}^{32\times 1}$are the neurons in the hidden layer, ${\mathrm{W}}_1\in {ℝ}^{12\times 64}$, ${\mathrm{W}}_2\in {ℝ}^{64\times 32}$ are the coefficient weight term matrices of the two FC-layers, $b_1\in {ℝ}^{64\times 1}$ and $b_2\in {ℝ}^{32\times 1}$ are the bias term, and $\mathsf{\sigma }(·)$ is an entry-wise sigmoid function [18].

(4)$\mathsf{\sigma }\left(\mathsf{u}\right)=\frac{1}{1+\exp \left(-\mathsf{u}\right)}.$

The sigmoid function is well bounded and allows for efficient computation of the gradient. Finally, the predicted surface potential associated with each $x_{\mathrm{i}}^{\prime }$ is computed by

(5)$\widehat{{\mathrm{y}}_{\mathrm{i}}}{=\mathsf{w}}^{\mathrm{T}}·{ \mathsf{h}}_{\mathrm{i}}^2+\mathsf{b}.$

Here, $w\in {ℝ}^{32\times 1}$ and $b\in ℝ$ are model coefficients and bias. $\widehat{{\mathrm{y}}_{\mathrm{i}}}\in ℝ$ is the predicted value of the ANN. Mean-Squared-Error (MSE) $\sum {\left({\mathrm{y}}_{\mathrm{i}}-\widehat{{\mathrm{y}}_{\mathrm{i}}}\right)}^2/\mathrm{n}$ [19,20] is used as the loss function, which is iteratively minimized with stochastic gradient descent [21].

Upon the completion of the training process, the analytic expression of the surface potential can be written as:

(6)$\widehat{{\mathrm{y}}_{\mathrm{i}}}(\mathrm{or} {\mathsf{\varphi }}_{\mathrm{s}}{)=\mathsf{w}}^{\mathrm{T}} \mathsf{\sigma }\left({\mathrm{W}}_2^{\mathrm{T}}·\mathsf{\sigma }\left({\mathrm{W}}_1^{\mathrm{T}}·{\mathrm{PR}(\mathsf{x}}_{\mathrm{i}}{)+\mathsf{b}}_1\right){+\mathsf{b}}_2\right)+\mathsf{b}.$

which is a concise model and can be efficiently evaluated.

2.4. Surface Potential Written in Verilog-A

To further verify the applicability of the framework in circuit simulation, the trained artificial neural network should be transformed into the form of Verilog-A [22], which is the commonly used hardware description language for MOSFET and other electronic components. Verilog-A is the analogy subset of Verilog-AMS [23], originally intended for modeling the behavior of analog and mixed-signal systems. Despite significant initial resistance, Verilog-A has emerged as the de facto stand language for defining and distributing compact models. In 2004, constructs explicitly for the purpose of compact modeling were added. Considering the incompatibility of matrix calculations in Verilog-A language, an automation script (Python [24], for example) is adopted to accelerate the transform process. Two steps are divided to realize this purpose. First, the value of the parameters in each layer should be entered into Verilog-A. In the framework, these parameters include physical parameters (for example, vacuum dielectric constant of silicon [25] ${\mathsf{\epsilon }}_{\mathrm{si}}$, Planck constant k, and Unit charge constant q) used in PRNN, Min and Max value for normalization, bias term $b_{\mathrm{i}}$, and weights term $w_{\mathrm{i}}$. Table 2 (I) shows the pseudo code [26] for inputting $w_{\mathrm{i}}$. The value of $w_{\mathrm{i}}$ is read from the saved txt file and written to Verilog-A by intermediate variable a. Then, in the second step, the forward propagation process of the artificial neural network is realized in Verilog-A. In this step, the implementation of the calculation process in the framework includes the data normalization, neurons (${\mathsf{h}}_{\mathrm{i}}$) in the hidden layers and denormalization of data at output data $\widehat{{\mathrm{y}}_{\mathrm{i}}}$. Table 2 (II) shows the pseudo code for transforming ${\mathsf{h}}_{\mathrm{i}}^2$. The calculation of weight and bias terms between each neural is conducted following Equations (3) and (4).

2.5. Establishing the Compact Model

After obtaining the analytical surface potential expression, the related compact model for MOSFET can be built. In this work, a semi-classical compact model is developed based on the combination of trained surface potential expression and the classical compact model. The main equations are shown as follows: [27,28,29,30,31]

(7)${\mathrm{I}}_{\mathrm{ds}}{=\mathrm{u}}_{\mathrm{eff}}{\mathrm{C}}_{\mathrm{ox}}\frac{\mathrm{W}}{\mathrm{L}}\left({\mathrm{V}}_{\mathrm{gf}}\left(\mathsf{\varphi }{\mathrm{s}}_{\mathrm{d}}-\mathsf{\varphi }{\mathrm{s}}_{\mathrm{s}}\right)-0.5\left(\mathsf{\varphi }{\mathrm{s}}_{\mathrm{d}}^2-\mathsf{\varphi }{\mathrm{s}}_{\mathrm{s}}^2\right)\right).$

(8)${\mathrm{u}}_{\mathrm{eff}}=\frac{{\mathrm{u}}_0}{1+{\mathrm{MUE}*\mathrm{E}}_{\mathrm{eff}}{}^{\mathrm{THEMU}}+\mathrm{CS}{\left(\frac{{\mathrm{q}}_{\mathrm{d}}}{{\mathrm{q}}_{\mathrm{d}}+{\mathrm{q}}_{\mathrm{i}}}\right)}^2}$

(9)${\mathrm{V}}_{\mathrm{gf}}=\mathrm{Log}\left[1+{\mathrm{e}}^{\left({\mathrm{V}}_{\mathrm{gs}}-{\mathrm{V}}_{\mathrm{fb}}\right)*\mathrm{Sl}}\right]/\mathrm{Sl}$

(10)$\mathsf{\varphi }{\mathrm{s}}_{\mathrm{s}}=\mathsf{\varphi }\mathrm{s}\left[{\mathrm{V}}_{\mathrm{gs}},{\mathrm{V}}_{\mathrm{ds}},\mathrm{T},\dots ,\mathrm{x}\left]-\mathsf{\varphi }\mathrm{s}\right[0,0,\mathrm{T},\dots ,\mathrm{x}\right]$

(11)$\mathsf{\varphi }{\mathrm{s}}_{\mathrm{d}}=\mathsf{\varphi }{\mathrm{s}}_{\mathrm{s}}+{\mathrm{V}}_{\mathrm{dsx}}$

(12)${\mathrm{V}}_{\mathrm{dsx}}={\mathrm{gV}}_{\mathrm{ds}}{\left(1+{\frac{{\mathrm{gV}}_{\mathrm{ds}}}{{\mathrm{V}}_{\mathrm{dsat}}}}^{\mathrm{m}}\right)}^{-\frac{1}{\mathrm{m}}}$

Here, ${\mathrm{u}}_{\mathrm{eff}}$ [29] is carrier mobility, ${\mathrm{u}}_0$ is carrier mobility at a low electrical field, ${\mathrm{q}}_{\mathrm{d}}$ is the normalized charge of the depletion region, ${\mathrm{q}}_{\mathrm{i}}$ is the normalized charge of the inversion region, (MUE,THEMU) is the fitting parameters accounting for the mobility degradation [32] caused by the surface roughness and phonon scattering. Coulomb scattering is introduced using the parameter CS. ${\mathrm{E}}_{\mathrm{eff}}$ denotes the effective vertical field at the potential midpoint. ${\mathrm{V}}_{\mathrm{gf}}$ [33] accounts for the subthreshold region with parameter Sl acting as the correction parameter to the subthreshold swing. $\mathsf{\varphi }{\mathrm{s}}_{\mathrm{s}}$ is the surface potential obtained from the ANN at x = 0.01 um. ${\mathrm{V}}_{\mathrm{dsat}}$ [31] is the saturation voltage with m acting as a fitting parameter.

The gate capacitance model is also necessary in circuit simulation and can be calculated as follows [29,34,35,36]:

(13)${\mathrm{Q}}_{\mathrm{g}}={\mathrm{W}*\mathrm{C}}_{\mathrm{ox}}{{\displaystyle \int }}_0^{\mathrm{L}}\left({\mathrm{V}}_{\mathrm{g}}-{\mathrm{V}}_{\mathrm{fb}}-\mathsf{\varphi }\mathrm{s}\left[{\mathrm{V}}_{\mathrm{gs}},{\mathrm{V}}_{\mathrm{ds}},\mathrm{T},\dots ,\mathrm{x}\right]\right)\mathrm{dx}$

(14)${\mathrm{Q}}_{\mathrm{d}}={\mathrm{W}*\mathrm{C}}_{\mathrm{ox}}{{\displaystyle \int }}_0^{\mathrm{L}}{\mathrm{q}}_{\mathrm{i}}\frac{\mathrm{y}}{\mathrm{L}}\mathrm{dx}$

(15)${\mathrm{Q}}_{\mathrm{S}}={\mathrm{W}*\mathrm{C}}_{\mathrm{ox}}{{\displaystyle \int }}_0^{\mathrm{L}}{\mathrm{q}}_{\mathrm{i}}\left(1-\frac{\mathrm{y}}{\mathrm{L}}\right)\mathrm{dx}$

(16)${\mathrm{C}}_{\mathrm{mn}}=-\frac{\partial {\mathrm{Q}}_{\mathrm{m}}}{\partial {\mathrm{V}}_{\mathrm{n}}},\mathrm{m}\ne \mathrm{n} ;{\mathrm{C}}_{\mathrm{mm}}=\frac{\partial {\mathrm{Q}}_{\mathrm{m}}}{\partial {\mathrm{V}}_{\mathrm{m}}}$

3. Method Validation and Discussion

We evaluated the proposed framework by computing the surface potential in 130 nm MOSFET. We generated 540,000 training samples and 100,000 testing samples by TCAD simulation. The d-dimensional device data $x_{\mathrm{i}}^{\prime }\mathrm{s}$ were generated by randomly sampling each variable from their feasible domains. The evaluation results are reported in Figure 3. The left coordinate in Figure 3 shows the relationship between the MSE testing error and the training iteration process. It can be found that during the training process, the MSE loss decreases and stabilizes at $9.58\times {10}^{-7}$, which is in millivolts, indicating a highly accurate result. The learning rate is an important hyper-parameter in the training process. A large learning rate promotes the rapid reduction of learning errors, while a small learning rate contributes to the convergence of the model. In this work, the learning rate is set to gradually decrease from 2 × 10⁻⁵ to 1 × 10⁻⁸ using the cosine annealing algorithm (a half cycle is adopted) during the training process, as the right coordinate in Figure 3 shows.

Figure 4a plots the 2D surface potential along the device channel. At a low gate voltage, the surface potential in the middle of the channel is determined by gate−channel work function differences. The surface potential of the drain and source terminal are raised by the PN junction[37], which is induced by different doping types of channel and source/drain terminals, and are hardly affected by ${\mathrm{V}}_{\mathrm{gs}}$. When ${\mathrm{V}}_{\mathrm{gs}}$ increases from 0 (V) to 1.4 (V), the surface potential in the channel increases due to the electrical field induced by gate voltage ${\mathrm{V}}_{\mathrm{gs}}$, while the potential at the drain/source terminal stays almost fixed. Thus, the minimum surface potential moves from the middle of the channel to the source terminal, which is a challenging feature that a traditional 1D Poisson equation [38] solution fails to capture. We found an excellent match between our model predictions and the TCAD simulation. Figure 4b plots the surface potential at the source and drain terminal versus the gate voltage, respectively. Excellent agreement is achieved between the TCAD simulation result and the PRNN result. When the gate voltage increases, the surface potential at the drain/source terminal increases first and then gradually saturates, which is consistent with previous reports [8].

Figure 5 plots the patterns of the minimum surface potential ($\mathsf{\varphi }{\mathrm{s}}_{\min }$), as well as the location of the minimum potential (x_min) along the channel; both w.r.t. drain voltage. It can be seen that the two patterns show an opposite trend; with the increase in drain terminal voltage, x_min moves to the source terminal and the $\mathsf{\varphi }{\mathrm{s}}_{\min }$ is increased, which is called the drain-induced barrier lowing (DIBL) effect. $\mathsf{\varphi }{\mathrm{s}}_{\min }$ decides the threshold voltage of the device according to Equation (8) [39].

(17) $\Delta {\mathrm{V}}_{\mathrm{t}}=-\mathsf{\eta }\Delta \mathsf{\varphi }{\mathrm{s}}_{\min }=-{\mathsf{\sigma }\mathrm{V}}_{\mathrm{ds}}.$

Here, $\mathsf{\eta }$ is the ideality factor and is assumed to be independent of bias condition. $\mathsf{\sigma }$ is a physical parameter that reflects the influence of ${\mathrm{V}}_{\mathrm{ds}}$ to threshold voltage. The DIBL effect causes an excess injection of the charge carrier into the channel and gives rise to an increased subthreshold current [40]. The overlaps of the gate depletion zone with the source/drain depletion zone share its depletion charge [41], and the shared charge is balanced by a counter charge distributed between the gate electrode and the source and drain contacts, which brings a shift in threshold voltage. With the introduction of the PRNN, analysis of the device against the DIBL effect could be conducted in a facile way, and thus facilitates the optimization of device performance.

Figure 6 shows the comparison of the developed surface potential based semi-classical compact and TCAD simulation results. Good agreement is achieved between the n-type transfer characteristic curve against different drain voltages (a), the output characteristic curve (b), the transfer characteristic curve against different operation temperatures [42], and (d) small signals gate capacitance ${\mathrm{C}}_{\mathrm{gg}}$. It shows that our model can well describe the device performance.

To further verify the applicability of the framework to modern microelectronic circuit design, the proposed compact model was transformed into Verilog-A and circuits simulation was conducted by including the MOSFET devices as new active components of the circuit simulator, as Figure 7 shows. A ring oscillator circuit with seven-stage inverters was connected in series to generate oscillation [43]. Figure 7a shows the Vout-vs-Vin curves of the inverter. When the size of the p-type MOSFET increases, the driver capability of the pull up increases, and thus, the Vout-vs-Vin curves shift to the right. Figure 7b shows the transient simulation results. When the size of the p-type MOSFET transistor decreases, the frequency of the oscillator decreases as well, and saturation appears at the lowest point of the oscillation. These simulation results clearly demonstrate the applicability and usefulness of our framework in circuit simulation applications.

Compared to the classical compact model method [29,44], the proposed framework avoids the numerical iteration process [14] in solving the surface potential expression, and thus, saves a great deal of effort in model design. Considering that most physical effects caused by device scaling directly act on surface potential, the proposed framework can better achieve underlying physic scaling compared to those works that directly train electrical properties of a device that is incompatible with model variation. Furthermore, in the literature [6], due to training data being obtained through the subtraction of device electrical properties and classical compact model output, the ANN acts as a correction term to existing models and contains scarcely underlying physical information. In contrast, the training data of the surface potential in this framework is obtained from TCAD simulators, which are based on equations of mathematical physics and reflect the physical relationship between device parameters and surface potential, thus containing more systematic physical information of the device.

4. Conclusions

We exploited the universal approximation power of artificial neural networks in learning from large amounts of simulation data to generate accurate, generalizable MOSFET compact models in a highly automated manner. Impressive results were reported in building the analytic surface potential of a 130 nm MOSFET, which proved to be of benefit in device optimization. Furthermore, our work reveals the great potential of modern artificial intelligence techniques in boosting microelectronic research. The accurate, generalizable, and automated compact model development not only reduces the gap between theory and computing, but it is also expected to bring new vigor to vast landscapes in design, simulation, and the optimization of very large-scale circuit systems.

Author Contributions

Conceptualization, writing—review and editing, funding acquisition, L.W.; Methodology, formal, software, validation, analysis, writing, investigation, writing—original draft preparation, S.H. All authors have read and agreed to the published version of the manuscript.

Data Availability Statement

The data presented in this study are available on request from the corresponding author.

Conflicts of Interest

The authors declare no conflict of interest.

Footnotes

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Figures and Tables

Figure 1. Schematic of the PRNN Framework. Stimulation data from TCAD is firstly transformed at the physical-relationship layer to contain more fundamental relations of physics. Then, the pretreated data is trained by fully-connected artificial neural networks.

Figure 2. Schematic of the 130 nm MOSFET device with a polysilicon gate stimulated in TCAD. The surface potential is defined as the difference between the substrate electrostatic potential and the electrostatic potential (one nanometer below the channel surface).

Figure 3. Mean Square Error (MSE) and learning rate with training iterations.

Figure 4. An excellent match between our PRNN model (lines) and the TCAD numerical simulation (symbols) for (a) the surface potential [Forumla omitted. See PDF.] along the device channel against different gate voltages and (b) the surface potential against the gate voltage at the source/drain terminal.

Figure 5. (a) The lowest potential ([Forumla omitted. See PDF.]) w.r.t. drain voltage changes and (b) the lowest surface potential location ([Forumla omitted. See PDF.]) andThe DIBL effect is observed for the shift of [Forumla omitted. See PDF.] and [Forumla omitted. See PDF.] with [Forumla omitted. See PDF.].

Figure 6. A good match between our MOSFET compact model (line) and the TCAD solution data (symbol) for (a) output characteristics, (b) transfer (both in conventional and logarithmic coordinates) characteristics, (c) transfer characteristics with different temperature, and (d) gate capacitance to gate voltage.

Figure 7. (a) The circuit diagram of a ring oscillator composed of seven-stage inverters connected in series; the inverter structure is shown at the bottom. The relation between V-out and V-in for the inverter: with the size of the p-type MOSFET pull up transistor increasing, the pull up driver capability increases as well, causing the curves to shift to the right. (b) Transient simulation results of the ring oscillator: with the size of the p-type MOSFET transistor decreasing, the frequency of the oscillator is reduced and saturation appears at the lowest point of oscillation.

Table 1

Features of stimulated device data ${\mathsf{x}}_{\mathrm{i}}$.

Term	Min Value	Max Value	Std
${\mathrm{V}}_{\mathrm{gs}}$ (V)	−1.4	1.4	0.81
${\mathrm{V}}_{\mathrm{ds}}$ (V)	0	1.4	0.418
T (K)	275	300	14.14
x (nm)	0	70	48.59
L (nm)	50	70	7.07
${\mathrm{N}}_{\mathrm{d}} ({\mathrm{cm}}^2$)	1 × 1017	1 × 1019	3.7 × 1018
${\mathsf{\varphi }}_{\mathrm{s}}$ (eV)	−0.08438	2.405	0.49443

Table 2

The pseudo code for transforming the ANN to Verilog-A language.

(I) Parameter Input for $w_{\mathrm{i}}$

for $w_{\mathrm{i}}$ in frameworkwith file.open($w_{\mathrm{i}}$_value.txt) as f1:

for line in f1.readlines():

line_list = line.split()for j in range(len(line_list)):

a = “parameter real $w_{\mathrm{i}}$” + str(i) + ’ = ‘+str(line_list[j]) + ’;’

f.write(a)i = i + 1i = 1

(II) Forward Propagation Realization for $h_2$

for i in range(1,len(hidden layer 2)):

a = ‘$h_2$’ + str(i) + ’ = ‘ + ’1/(1 + exp(-(‘

for j in range(1,len(hidden layer 1)):

a = a + ’$w_2$’ + str(i) + str(j) + ’*$h_1$’ + str(j) + ’ + ’

a = a + ’$b_2$’ + str(i) + ’;’    f.write(a)

References

1. Rios, R.; Mudanai, S.; Shih, W.-K.; Packan, P. An efficient surface potential solution algorithm for compact MOSFET models. Proceedings of the IEDM Technical Digest. IEEE International Electron Devices Meeting; San Francisco, CA, USA, 13–15 December 2004; pp. 755-758.

2. Brews, J.R. A charge-sheet model of the MOSFET. Solid State Electron.; 1978; 21, pp. 345-355. [DOI: https://dx.doi.org/10.1016/0038-1101(78)90264-2]

3. Cham, K.M.; Oh, S.-Y.; Moll, J.L.; Lee, K.; Vande Voorde, P.; Chin, D. Numerical Simulation Systems. Computer-Aided Design and VLSI Device Development; Springer: Berlin/Heidelberg, Germany, 1988; pp. 13-21.

4. Wang, J.; Kim, Y.H.; Ryu, J.; Jeong, C.; Choi, W.; Kim, D. Artificial Neural Network-Based Compact Modeling Methodology for Advanced Transistors. IEEE Trans. Electron Devices; 2021; 68, pp. 1318-1325. [DOI: https://dx.doi.org/10.1109/TED.2020.3048918]

5. Habal, H.; Tsonev, D.; Schweikardt, M. Compact Models for Initial MOSFET Sizing Based on Higher-order Artificial Neural Networks. Proceedings of the 2020 ACM/IEEE 2nd Workshop on Machine Learning for CAD (MLCAD); Virtual Event Iceland, 16–20 November 2020; pp. 111-116.

6. Kao, M.-Y.; Kam, H.; Hu, C. Deep-learning-assisted physics-driven MOSFET current-voltage modeling. IEEE Electron Device Lett.; 2022; 43, pp. 974-977. [DOI: https://dx.doi.org/10.1109/LED.2022.3168243]

7. Abiodun, O.I.; Jantan, A.; Omolara, A.E.; Dada, K.V.; Mohamed, N.A.; Arshad, H. State-of-the-art in artificial neural network applications: A survey. Heliyon; 2018; 4, e00938. [DOI: https://dx.doi.org/10.1016/j.heliyon.2018.e00938] [PubMed: https://www.ncbi.nlm.nih.gov/pubmed/30519653]

8. Sharma, R.K.; Gupta, M.; Gupta, R.S. TCAD assessment of device design technologies for enhanced performance of nanoscale DG MOSFET. IEEE Trans. Electron Devices; 2011; 58, pp. 2936-2943. [DOI: https://dx.doi.org/10.1109/TED.2011.2160065]

9. Gnudi, A.; Ventura, D.; Baccarani, G.; Odeh, F. Two-dimensional MOSFET simulation by means of a multidimensional spherical harmonics expansion of the Boltzmann transport equation. Solid-State Electron.; 1993; 36, pp. 575-581. [DOI: https://dx.doi.org/10.1016/0038-1101(93)90269-V]

10. Ortiz-Conde, A.; Sánchez, F.G.; Guzmán, M. Exact analytical solution of channel surface potential as an explicit function of gate voltage in undoped-body MOSFETs using the Lambert W function and a threshold voltage definition therefrom. Solid-State Electron.; 2003; 47, pp. 2067-2074. [DOI: https://dx.doi.org/10.1016/S0038-1101(03)00242-9]

11. Neamen, D.A. Semiconductor Physics and Devices: Basic Principles; McGraw-Hill: New York, NY, USA, 2003.

12. Hamid, H.A.E.; Guitart, J.R.; Iniguez, B. Two-Dimensional Analytical Threshold Voltage and Subthreshold Swing Models of Undoped Symmetric Double-Gate MOSFETs. IEEE Trans. Electron Devices; 2007; 54, pp. 1402-1408. [DOI: https://dx.doi.org/10.1109/TED.2007.895856]

13. Minton, S.; Carbonell, J.G.; Knoblock, C.A.; Kuokka, D.R.; Etzioni, O.; Gil, Y. Explanation-based learning: A problem solving perspective. Artif. Intell.; 1989; 40, pp. 63-118.

14. Yu, B.; Lu, H.; Liu, M.; Taur, Y. Explicit Continuous Models for Double-Gate and Surrounding-Gate MOSFETs. IEEE Trans. Electron Devices; 2007; 54, pp. 2715-2722. [DOI: https://dx.doi.org/10.1109/TED.2007.904410]

15. Patro, S.; Sahu, K. Normalization: A preprocessing stage. arXiv; 2015; arXiv: 1503.06462[DOI: https://dx.doi.org/10.17148/IARJSET.2015.2305]

16. Zhou, Z.-H. Machine Learning; Springer Nature: Berlin/Heidelberg, Germany, 2021.

17. Zhang, Z. Artificial Neural Network; Springer: Cham, Switzerland, 2018; pp. 1-35.

18. Jain, A.K.; Mao, J.; Mohiuddin, K.M. Artificial neural networks: A tutorial. Computer; 1996; 29, pp. 31-44. [DOI: https://dx.doi.org/10.1109/2.485891]

19. Christoffersen, P.; Jacobs, K. The importance of the loss function in option valuation. J. Financ. Econ.; 2004; 72, pp. 291-318. [DOI: https://dx.doi.org/10.1016/j.jfineco.2003.02.001]

20. Wallach, D.; Goffinet, B. Mean squared error of prediction as a criterion for evaluating and comparing system models. Ecol. Model.; 1989; 44, pp. 299-306. [DOI: https://dx.doi.org/10.1016/0304-3800(89)90035-5]

21. Amari, S.-I. Backpropagation and stochastic gradient descent method. Neurocomputing; 1993; 5, pp. 185-196. [DOI: https://dx.doi.org/10.1016/0925-2312(93)90006-O]

22. McAndrew, C.C.; Coram, G.J.; Gullapalli, K.K.; Jones, J.R.; Nagel, L.W.; Roy, A.S.; Roychowdhury, J.; Scholten, A.J.; Smit, G.D.; Wang, X.J. Best practices for compact modeling in Verilog-A. IEEE J. Electron Devices Soc.; 2015; 3, pp. 383-396.

23. Christen, E.; Bakalar, K. VHDL-AMS-a hardware description language for analog and mixed-signal applications. IEEE Trans. Circuits Syst. II Analog Digit. Signal Process.; 1999; 46, pp. 1263-1272. [DOI: https://dx.doi.org/10.1109/82.799677]

24. Van Rossum, G. Python Reference Manual; CWI: Nampa, ID, USA, 1995.

25. Han, S.M.; Aydil, E.S. Reasons for lower dielectric constant of fluorinated SiO₂ films. J. Appl. Phys.; 1998; 83, pp. 2172-2178. [DOI: https://dx.doi.org/10.1063/1.366955]

26. Bellamy, R.K.E. What does pseudo-code do? A psychological analysis of the use of pseudo-code by experienced programmers. Hum.–Comput. Interact.; 1994; 9, pp. 225-246. [DOI: https://dx.doi.org/10.1207/s15327051hci0902_3]

27. Bucher, M.; Lallement, C.; Enz, C.; Krummenacher, F. Accurate MOS modelling for analog circuit simulation using the EKV model. Proceedings of the 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World, ISCAS 96; Atlanta, GA, USA, 15 May 1996; Volume 704, pp. 703-706.

28. Lee, C.S.; Pop, E.; Franklin, A.D.; Haensch, W.; Wong, H.S.P. A Compact Virtual-Source Model for Carbon Nanotube FETs in the Sub-10-nm Regime—Part I: Intrinsic Elements. IEEE Trans. Electron Devices; 2015; 62, pp. 3061-3069. [DOI: https://dx.doi.org/10.1109/TED.2015.2457453]

29. Gildenblat, G.; Li, X.; Wu, W.; Wang, H.; Jha, A.; Langevelde, R.V.; Smit, G.D.J.; Scholten, A.J.; Klaassen, D.B.M. PSP: An Advanced Surface-Potential-Based MOSFET Model for Circuit Simulation. IEEE Trans. Electron Devices; 2006; 53, pp. 1979-1993. [DOI: https://dx.doi.org/10.1109/TED.2005.881006]

30. Pei, G.; Ni, W.; Kammula, A.V.; Minch, B.A.; Kan, E.-C. A physical compact model of DG MOSFET for mixed-signal circuit applications-part I: Model description. IEEE Trans. Electron Devices; 2003; 50, pp. 2135-2143.

31. Ytterdal, T.; Cheng, Y.; Fjeldly, T.A. MOSFET device physics and operation. Device Modeling for Analog and RF CMOS Circuit Design; John Wiley and Sons: Hoboken, NJ, USA, 2003; pp. 1-45.

32. Esseni, D.; Abramo, A. Modeling of electron mobility degradation by remote Coulomb scattering in ultrathin oxide MOSFETs. IEEE Trans. Electron Devices; 2003; 50, pp. 1665-1674. [DOI: https://dx.doi.org/10.1109/TED.2003.814973]

33. Ghibaudo, G.; Aouad, M.; Cassé, M.; Martinie, S.; Poiroux, T.; Balestra, F. On the modelling of temperature dependence of subthreshold swing in MOSFETs down to cryogenic temperature. Solid-State Electron.; 2020; 170, 107820. [DOI: https://dx.doi.org/10.1016/j.sse.2020.107820]

34. Zong, Z.; Li, L.; Jang, J.; Lu, N.; Liu, M.J. Analytical surface-potential compact model for amorphous-IGZO thin-film transistors. J. Appl. Phys.; 2015; 117, 215705. [DOI: https://dx.doi.org/10.1063/1.4922181]

35. Park, H.-J.; Ko, P.K.; Hu, C. A charge sheet capacitance model of short channel MOSFETs for SPICE. IEEE Trans. Comput.-Aided Design Integr. Circuits Syst.; 1991; 10, pp. 376-389. [DOI: https://dx.doi.org/10.1109/43.67791]

36. Elmasry, M.I. Capacitance calculations in MOSFET VLSI. IEEE Electron Device Lett.; 1982; 3, pp. 6-7. [DOI: https://dx.doi.org/10.1109/EDL.1982.25454]

37. Elamaran, D.; Suzuki, Y.; Satoh, H.; Banerjee, A.; Hiromoto, N.; Inokawa, H.J.M. Performance comparison of SOI-based temperature sensors for room-temperature terahertz antenna-coupled bolometers: MOSFET, PN junction diode and resistor. Micromachines; 2020; 11, 718. [DOI: https://dx.doi.org/10.3390/mi11080718]

38. Guo, J.; Zhao, Y.; Yang, G.; Chuai, X.; Lu, W.; Liu, D.; Chen, Q.; Duan, X.; Huang, S.; Su, Y. A new surface potential based compact model for independent dual gate a-IGZO TFT: Experimental verification and circuit demonstration. Proceedings of the 2020 IEEE International Electron Devices Meeting (IEDM); San Francisco, CA, USA, 12–18 December 2020; pp. 22.26.21-22.26.24.

39. Fjeldly, T.A.; Shur, M. Threshold voltage modeling and the subthreshold regime of operation of short-channel MOSFETs. IEEE Trans. Electron Devices; 1993; 40, pp. 137-145. [DOI: https://dx.doi.org/10.1109/16.249436]

40. Chamberlain, S.G.; Ramanan, S. Drain-induced barrier-lowering analysis in VSLI MOSFET devices using two-dimensional numerical simulations. IEEE Trans. Electron Devices; 1986; 33, pp. 1745-1753. [DOI: https://dx.doi.org/10.1109/T-ED.1986.22737]

41. Dargar, A.; Srivastava, V.M. Thickness modeling of short-channel cylindrical surrounding double-gate MOSFET at strong inversion using depletion depth analysis. Micro Nanosyst.; 2021; 13, pp. 319-325. [DOI: https://dx.doi.org/10.1109/T-ED.1986.22737]

42. Osman, A.A.; Osman, M.A. Investigation of high temperature effects on MOSFET transconductance (g/sub m/). Proceedings of the 1998 the 4th International High Temperature Electronics Conference. HITEC (Cat. No. 98EX145); Albuquerque, NM, USA, 14–18 June 1998; pp. 301-304.

43. Srivastava, N.A.; Priya, A.; Mishra, R.A. Design and analysis of nano-scaled SOI MOSFET-based ring oscillator circuit for high density ICs. Appl. Phys. A; 2019; 125, 533. [DOI: https://dx.doi.org/10.1007/s00339-019-2828-x]

44. Duarte, J.P.; Khandelwal, S.; Medury, A.; Hu, C.; Kushwaha, P.; Agarwal, H.; Dasgupta, A.; Chauhan, Y.S. BSIM-CMG: Standard FinFET compact model for advanced circuit design. Proceedings of the ESSCIRC Conference 2015—41st European Solid-State Circuits Conference (ESSCIRC); Graz, Austria, 14–18 September 2015; pp. 196-201.