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Abstract

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The article discusses the design stages of very large-scale integrated circuits (VLSI) and the features of the procedure for verifying complex-functional VLSI blocks. The main approaches to microcircuit verification procedures are analyzed to minimize the duration of verification cycles. In practice, a combination of several approaches to verification is usually used.

Details

1009240
Subject
Very large scale integration;
Design standards;
Verification;
Circuit design;
Integrated circuits;
Software;
Semiconductors
Location
Russia
Identifier / keyword
Very Large Scale Integration; Computer-aided design; Nanolithography
Title
Verification methods for complex-functional blocks in CAD for chips deep submicron design standards
Author
Zolnikov, Vladimir; Zolnikov, Konstantin; Ilina, Nadezhda; Grabovy, Kirill
Publication title
E3S Web of Conferences; Les Ulis
Volume
376
Source details
International Scientific and Practical Conference “Environmental Risks and Safety in Mechanical Engineering” (ERSME-2023)
Publication year
2023
Publication date
2023
Section
I Environmental Risks and Safety in Mechanical Engineering
Publisher
EDP Sciences
Place of publication
Les Ulis
Country of publication
France
Publication subject
Sciences: Comprehensive Works
ISSN
25550403
e-ISSN
22671242
Source type
Conference Paper
Language of publication
English
Document type
Conference Proceedings
Publication history
 
 
Online publication date
2023-03-31
Publication history
 
 
   First posting date
31 Mar 2023
DOI
https://doi.org/10.1051/e3sconf/202337601090
ProQuest document ID
2793408499
Document URL
https://www.proquest.com/conference-papers-proceedings/verification-methods-complex-functional-blocks/docview/2793408499/se-2?accountid=208611
Copyright
© 2023. This work is licensed under https://creativecommons.org/licenses/by/4.0/ (the “License”). Notwithstanding the ProQuest Terms and conditions, you may use this content in accordance with the terms of the License.
Last updated
2025-03-28
Database
ProQuest One Academic