The Optimization of Program Operation for Low Power Consumption in 3D Ferroelectric (Fe)-NAND Flash Memory

Abstract

This paper proposes an optimized program operation method for ferroelectric NAND (FE-NAND) flash memory utilizing the gate-induced drain leakage (GIDL) program and validated through simulations. The program operation was performed by setting the time for the unselected cell to reach the pass voltage (V_pass) to 0.1 µs, 0.2 µs, and 0.3 µs, respectively. As the time for the unselected word line (WL) to reach V_pass increases, the channel potential increases due to a decrease in the electron–hole recombination rate. After the program operation, the threshold voltage (V_th) shift of the selected cell and the pass disturb of the unselected cells according to the V_pass condition were analyzed. Consequently, there was a more significant change in V_th among selected cells compared to the time for unselected cells to reach V_pass as 0.1 µs. The findings of this study suggest an optimal program operation that increases slowly and decreases rapidly through the variation of V_th according to the program operation. By performing the proposed program operation, we confirmed that low-power operation is achievable by reducing the WL voltage by 2 V and the bit line (BL) voltage by 1 V, in contrast to the conventional GIDL program.

1. Introduction

Semiconductor technology is pivotal in modern society, serving as an indispensable foundation across diverse fields. As the demand for semiconductors continues to surge, NAND flash memory technology and performance are constantly evolving, with innovations that encompass enhanced speed, increased density, and reduced power consumption [1,2,3,4,5,6,7,8,9]. Nevertheless, 2D NAND flash memory is continuously being replaced by 3D NAND flash memory due to technical obstacles such as limited cell density, interference, finite lifespan, and persistent downscaling challenges [10,11,12,13,14]. Moreover, 3D NAND flash memory surpasses 2D NAND flash memory in both performance and capacity, and researchers continue to explore new structures and innovative technologies in the realm of 3D NAND flash memory [15]. The introduction of FE-NAND flash memory aimed to address the issue of high program voltage (V_PGM) associated with the charge-trap flash (CTF) structure [16,17]. Ferroelectric field-effect transistors (FE-FETs) fabricated using hafnia-based ferroelectrics are attracting attention as next-generation memory devices due to their low operating voltage, excellent data retention, and fast switching speed.

It has intrinsic, non-volatile memory properties due to its two stable polarization states that can be switched. In addition, it has the advantage of being compatible with existing complementary metal oxide semiconductor manufacturing processes, and the conformal deposition of ferroelectric films is possible even in vertical structures such as 3D NAND flash memory through atomic layer deposition. Accordingly, research is continuing on 3D FE-NAND flash memory, which adds a ferroelectric thin film to the gate stack of existing NAND flash cells [18]. This study is concerned with the GIDL erase method employed in the CTF structure that was adapted for use in the program operation of FE-NAND flash memory cells [19]. Implementing the GIDL program makes it feasible to perform normal memory operations while maintaining the conventional 3D NAND flash memory structure and wiring method despite the distinctive operational traits of FE-NAND. Furthermore, even in multi-string operation, GIDL can be selectively generated for the BL to be programmed, thereby enabling the same program operation as the conventional 3D NAND flash memory structure.

In this study, we employed the Synopsys Sentaurus Technology computer-aided design (TCAD) tool to analyze the V_th of the selected cell and the pass disturb of the unselected cell, depending on the time required for the unselected WL to reach the V_pass during the GIDL program operation [20]. In addition, we proposed optimal voltage conditions for the program operation proposed here. Therefore, we confirmed that low-power program operation is achieved by reducing the WL voltage by 2 V and the BL voltage by 1 V, compared with the conventional GIDL program.

2. Structure of the Proposed Program Operation

Figure 1 shows a cross-sectional view of FE-NAND flash memory, which was generated using Synopsys Sentaurus structure editor. The configuration includes memory transistors for WL₀, WL₁, and WL₂, along with string select line (SSL) and ground select line (GSL) transistors. Here, WL₁ represents the selected cell. As detailed in Figure 1 and in Table 1, the structure comprises SiO₂, Poly-Si, HfO₂, and a metal gate. The cross-section in Figure 1 was simulated as a gate-all-around (GAA) structure using the cylindrical command. In addition, models were employed to consider doping concentration dependence, high field saturation, trap scattering mobility, and Trap-Assist-Tunnel (TAT) effects in the device simulations. Also, simulations of the V-NAND structure’s operation included the utilization of Shockley–Read–Hall (SRH), Schenk band-to-band recombination, and tunneling models.

Figure 2 shows a voltage–timing diagram for each node employed in the GIDL program operation of the FE-NAND flash memory. The duration for the unselected cell to reach V_pass was configured as follows: Case 1 with 0.1 µs, Case 2 with 0.2 µs, and Case 3 with 0.3 µs. When a voltage of V_PGM = 10 V is applied to the selected BL and V_cc = 2 V is applied to the SSL, the channel potential increases. Selective programming was achieved by applying GND to the selected WL, V_pass = 7 V to the unselected WL, and GND to the GSL.

3. Simulation Results

Figure 3a shows the channel potential of the selected string at 0.5 µs during program operation in Case 1, Case 2, and Case 3. The channel potential of the selected string increases sequentially in the order of Case 1, Case 2, and Case 3. Figure 3b presents the channel recombination rates in Case 1, Case 2, and Case 3 during the program operation at 0.1 µs. This explains why the channel potential is highest in Case 3 [21,22,23]. In Case 1, the recombination rate is the highest, and it progressively decreases towards Case 2 and Case 3. When the unselected cell operates at 0.1 µs, Case 3 exhibits the lowest V_pass. A higher V_pass leads to a reduction in electron and hole density within the channel due to recombination, ultimately resulting in a decrease in the channel potential.

Figure 4a represents the I−V curve of the selected cell (WL₁) measured at 0.6 µs after programming in all cases. V_th increases from 1.789 V in Case 1 to 2.211 V in Case 3. As the channel potential increases during the GIDL program, the potential difference with the selected cell also increases, resulting in it being most programmed in Case 3. Figure 4b,c show the pass disturb of unselected cells (WL₀, WL₂) measured at 0.6 µs after program operation in all cases [24,25,26]. The V_th shifted more in both adjacent cells from Case 1 to Case 2 and Case 3. In the Case 3 programming, a pass disturb of 0.18 V was observed in WL₀, and a pass disturb of 0.17 V occurred in WL₂.

The following results were obtained by comparing to the conventional method of 0.5 µs. In this case, the time for the unselected cell to reach V_pass was fixed at 0.1 µs, and then the timing at which V_pass decreases was varied to 0.3 µs and 0.4 µs. This approach is in contrast to the proposed program operation method.

Figure 5a represents the I−V curve of the selected cell, measured at 0.6 µs after programming in all cases. As previously mentioned, it was confirmed that there was no effect on V_th, as the recombination rate remained consistent. Figure 5b presents the pass disturb of an unselected cell, measured at 0.6 µs after program operation in all cases. Based on the measurement results, the most significant shift in V_th occurs when V_pass decreases at 0.3 µs. As the decrease time becomes faster, a smaller value of V_pass is applied within the same time frame. This results in an increased potential difference, subsequently leading to a higher pass disturb.

Hence, in contrast to the proposed program operation method, an analysis conducted at various time points when V_pass decreases after reaching the unselected cell revealed that the shift in the V_th of the selected cell had a negligible impact, while the pass disturb due to a substantial V_th shift in the unselected cell had a significant effect.

It has been confirmed that low-power program operation is achievable by implementing Case 3, as proposed in this paper. Therefore, the optimal BL/WL voltage conditions during low-power program operation were found by analyzing the program of the selected cell and the disturb of the adjacent unselected cell while reducing it by 1 V increments using TCAD simulation.

Figure 6a,b show the Case 3 timing graph and table of the disturbance of the V_th of the selected cell and the adjacent unselected cell during the program operation according to the WL/BL voltage by applying the Case 3 method. In the Case 1 program operation, where the time for the unselected cell to reach V_pass is 0.1 µs, corresponding to conventional GIDL program operation, the V_th of WL₁ is 1.789 V, and the V_th shift due to disturb on WL₀ and WL₂ is 0.129 V and 0.135 V, respectively. Subsequent TCAD simulations confirmed that WL = 5 V and BL = 9 V are the optimal voltage conditions for low-power program operation in the proposed Case 3 during GIDL program operation.

In Figure 7a,b, a comparison is made between the selected cell and I−V curves of WL₀ and WL₂ under the conditions of BL = 10 V and WL = 7 V, representing Case 1, which corresponds to conventional GIDL program conditions, which were made after program operation was performed in Case 3 under the conditions of BL = 9 V and WL = 5 V.

As depicted in Figure 7a, it is evident that there is nearly the same degree of change in V_th. Specifically, V_th = 1.792 V is observed during optimal voltage condition program operation using the Case 3 method, whereas V_th = 1.789 V is seen during conventional GIDL program operation. Furthermore, Figure 7b presents a graph comparing the application of an optimal voltage in the programming process using the Case 3 method with the pass disturb of the unselected cell adjacent to the conventional GIDL program. The analysis revealed that the program disturb increased compared to the conventional GIDL program. However, the increase in disturb, approximately 0.05 V, does not pose significant operational issues. Therefore, the proposed program operation has optimized low-power functionality compared to the conventional FE-NAND operation [19].

4. Conclusions

In this study, to optimize the programming method in the 3D FE-NAND flash memory structure, the GIDL program was applied. The voltage applied to the unselected cell was then analyzed under different cases. With an increase in the time it takes for the unselected cell to reach V_pass, the electron–hole recombination rate decreases while the channel potential increases. Consequently, the V_th of the selected cell increased, and the pass disturb of the unselected cell also escalated. In conclusion, we confirmed that the program effect is most pronounced in Case 3, characterized by the increase of channel potential. On the contrary, it was observed that as the time for the voltage to drop after reaching V_pass increases, there is a corresponding increase in the occurrence of pass disturb. Hence, it was established that controlling the V_pass time to slowly increase and rapidly decrease yielded the optimal outcome for low-power program operation. Subsequently, following the optimized programming method, BL/WL voltage was reduced by 1 V through TCAD simulation. As a result of these simulations, it was affirmed that low-power program operation could be achieved by lowering the WL voltage by 2 V and the BL voltage by 1 V compared to the conventional GIDL program operation. Therefore, it is expected that this study will make effective contributions when transitioning from the CTF V-NAND structure to the FE-NAND structure in the future.

Author Contributions

Methodology, paper writing, investigation, conceptualization, M.Y. and G.L.; validation and investigation, M.Y., G.L., G.R. and H.K.; project administration, funding acquisition, editing, and supervision, M.K. All authors have read and agreed to the published version of the manuscript.

Data Availability Statement

Data is contained within the article.

Conflicts of Interest

The authors declare no conflicts of interest.

Footnotes

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Figures and Table

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Figure 1. Cross-sectional view of the 3D FE-NAND structure.

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Figure 2. The program operation of the FE-NAND flash memory using GIDL.

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Figure 3. Phenomenon in the channels during the operation of the program for Case 1 (BL = 10 V, WL = 7 V), Case 2 (BL = 10 V, WL = 7 V), and Case 3 (BL = 10 V, WL = 7 V): (a) selected string channel potential (b) for each case channel recombination rate at 0.1 µs.

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Figure 4. Comparison of I−V curves for different proposed Cases: (a) changes in the Vth of the selected cell; (b,c) changes in pass disturb for adjacent unselected cells.

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Figure 5. Comparison of I−V curves based on the decreasing time while keeping Vpass arrival time fixed at 1 μs: (a) changes in the Vth of the selected cell; (b) changes in pass disturb for unselected cells.

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Figure 6. A simulation measuring program and disturb while gradually reducing WL and BL voltages by 1 V each, using the optimized approach: (a) Case 3; (b) table. The table indicated the optimal voltage conditions.

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Figure 7. Comparison of I−V curves between Conventional Case 1 (BL = 10 V, WL = 7 V) and the optimized approach, Case 3 (BL = 10 V, WL = 7 V): (a) changes in the Vth of the selected cell; (b) changes in pass disturb for unselected cells.

Table 1

Parameters of FE-NAND.

Parameters	Value
SiO2 thickness	20 nm
Poly-Si channel thickness	20 nm
HfO2 thickness	10 nm
Gate length (WL, SSL, GSL)	40 nm
Spacer length	40 nm
Selected cell	WL1

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