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This dissertation describes the author's research in (1) the design and development of small general purpose bit-slice emulators; (2) model formulation of networks using small processors or bit-slice emulators; (3) performance evaluation of the resultant network models; and (4) design methods for evaluation of these network structures.
Networks of small processing elements can have unlimited variety. Out of the many possible multiprocessing architectures, we have proposed three models to study in this dissertation. These models treat von Neumann and non-von Neumann structures and provide a basis for the analysis and performance evaluation of vartons parallel configurations of small LSI processing elements, such as microprogrammable bit-slice devices. The three parallel architecture models analyzed are (1) the controlled multiserver model; (2) the array model; and (3) the data flow model.
The general purpose bit-slice emulator developed at New Mexico State University is used in the network models. The bit-slice emulator is very versatile and therefore can easily be modified to fit various requirements. Analytic and simulation techniques are employed in this study. For some models, both micro and macro analyses are performed. At the macro level, the analysis is carried out at the job level, whereas at the micro level the analysis is concerned with the behavior of the system at the instruction execution level.
Our intent is not to compare these models nor expect them to be universally applicable, but to provide building blocks and various approaches. We believe that this contribution will assist network researchers in effectively constructing and evaluating their own particular network models.