Pipelining of IIR lattice and wave digital filters

One of the most interesting aspects of digital signal processing is the wide variety of applications. These applications require diverse specifications for digital filters. For example, some applications may require high speed, while others may require low-power consumption, and yet some others may require low-sensitivity structures. To meet these diverse requirements more effectively, it is important to achieve pipelining of low-sensitivity recursive digital filter structures. However, implementation of high-speed, pipelined, recursive digital filters was considered impossible before because of the feedback loops. Only recently, scattered look-ahead technique was proposed to convert a nonpipelined direct form recursive filter to a pipelinable form. This technique, for the first time, made it feasible to implement high speed recursive digital filters using pipelining.

One of the important class of recursive digital filters with good finite word-length properties and suitable properties for VLSI implementation is the lattice IIR digital filters. In this thesis, the pipelining of basic, normalized, scaled normalized and orthogonal double-rotation digital lattice filters is proposed using the Schur algorithm and the constrained filter design methods. Another important class of recursive filters with low sensitivity is the WDF (Wave Digital Filter). The pipelining of WDFs is also presented.

The scaling method using SVD (State Variable Description) is very useful in analyzing finite word-length effects of digital filters. However, it is difficult to apply the method to a filter with nonstate variable nodes such as lattice filters or WDFs. To overcome this difficulty, URS (Upsampled & Retimed SVD) scaling method is proposed. Also, the scaled normalized lattice filter structure is derived using this method.

Finite word-length effects of most recursive digital filters become worse when the filter has sharp-transition. Low-noise and high-speed implementation method for these filters is proposed using DIFIR (Decomposed & Interpolated FIR) method.

The issue of low-power implementation is of great concern due to the increasing demand for high performance portable products. It is demonstrated that the low-power recursive lattice or WDFs can be implemented with CMOS technology using our pipelining method.