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Abstract
A new process-independent method for the automatic synthesis of sequencers from a path expression description is presented. Previous work in the area of sequencer synthesis has used methods that are applicable only to a certain method of chip manufacturing; for example, mutual exclusion can be accomplished with special nMOS cells. This research focuses on a methodology for constructing a sequencer in a way that is more independent of the chip implementation.
The designer indicates the desired specifications in the form of a path expression. This is an ordinary text file that he or she would create with an editor. An outline of path expressions is presented, including algorithms for testing for equivalency, deadlock, conflicts, and redundancy. The system presented here reads path expressions as input, and converts the expressions into an internal directed graph. The graph is then traversed and the structure of the graph is used to generate the required hardware.
The output file can then be easily translated into one of the forms suitable for implementation with vendor-supplied tools. The output is suitable for use as input to a CAD system to generate field programmable gate arrays, custom chips, or other hardware.
The turn around time for synthesis done in this way is on the order of a few minutes, as opposed to possibly several weeks for a custom implementation. Once the design is finalized, application specific chips can be manufactured if quantities dictate.
