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Abstract
Most computers that support virtual memory translate virtual addresses to physical addresses using a translation lookaside buffer (TLB) and a page table. Time spent in TLB miss handling--number of TLB misses times average TLB miss penalty--is increasing due to workload, architectural, and technological trends. This thesis studies TLB architectures that reduce the number of TLB misses by increasing TLB reach--the maximum address space mapped by a TLB--and page table designs that decrease TLB miss penalty or support new TLB architectures without increasing TLB miss penalty.
First, this thesis evaluates two TLB architectures in commercial use--superpages and complete subblocking. This thesis studies the benefits of superpages and the issues involved in modifying operating systems and page tables to support superpages. Complete subblocking allows processor designers to use larger chip areas to build large TLBs within cycle time constraints. Simulation results show that for comparable chip area, complete-subblock TLBs have faster access times and incur fewer TLB misses than single-page-size TLBs without requiring operating system changes.
Second, this thesis proposes a new TLB architecture, partial subblocking, that combines the best features of complete subblocking and superpages. Simulation results show that superpage and subblock TLBs, for comparable chip area, incur fewer TLB misses than single-page-size TLBs. Further, partial-subblock TLBs require simpler operating systems and incur fewer misses than superpage TLBs.
Third, superpage and partial-subblock TLBs are ineffective without operating system support. This thesis identifies the policies and mechanisms required to support these TLBs. In particular, this thesis proposes a physical memory allocation algorithm, page reservation, that makes partial-subblock TLBs effective or eliminates page copying in superpage creation.
Fourth, this thesis suggests modifications to conventional page tables to support superpage and subblock TLBs and proposes a new page table structure, clustered page table, that augments hashed page tables with subblocking. Simulation results show that clustered page tables are smaller and have a faster access time than conventional page tables when using single-page-size TLBs. A clustered page table improves on these advantages when storing superpage and subblock PTEs.
