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Abstract
Pipelined analog-to-digital converters (ADCs) are an integral part of a variety of systems, such as wireless transceivers and digital imaging. Many of these systems are used in portable devices, such as cell phones, where lowering the power consumption of the ADC would mean the ability to add new functionality or improve battery life. For these reasons, there is continuous interest in lowering the power of pipelined ADCs.
Within a pipelined ADC, the residue amplifiers consume the majority of the power. In typical implementations, closed-loop precision op-amp circuits are used for the residue amplifiers. Closed-loop op-amp circuits offer good signal accuracy, but are complex and power hungry. In an effort to lower the power of the residue amplifier and the entire pipelined ADC, this thesis presents a new dynamic source follower amplifier. The dynamic amplifier does not use a constant bias current, and the majority of the power consumed is delivered directly to the load. This results in better efficiency and lower overall power than traditional op-amp circuits.
A prototype pipelined ADC using dynamic source follower residue amplifiers was fabricated in a 90-nm CMOS process as a proof-of-concept. The resulting 9.4-bit ADC operates at sampling speeds of 50 MHz while consuming only 1.44 mW. The resulting figure of merit is 119 fJ/conv-step, which is comparable to the best state-of-the-art designs. These results demonstrate that the dynamic source follower amplifier is a viable alternative to traditional closed-loop op-amp based residue amplifiers and shows promise as a new architecture for future low-power ADCs.
