Content area
Abstract
Variations in clock signal delays could lead to significant reliability and performance problems in digital systems. International Technology Roadmap for Semiconductors [ITRS] identifies variability as a significant challenge in sub-65nm technologies. Increased die size and complexity of Deep Submicron SoCs, with technology scaling make it difficult to meet the timing requirements of all integrated components. As the level of integration of processors, memory and peripheral components on a single chip increases, conventional worst case design approaches with increased timing margins lead to significant limitations to system performance, thus emphasizing the need for more aggressive variability tolerant clocking techniques.
In this thesis, we study different techniques to address the variability problem in clock networks and propose a new on-line skew compensation technique that helps in overcoming the effects of variability in clock networks. This approach manipulates clock signal delays, using a reference signal from hierarchically higher level in the clock tree, and equalizes the clock arrival times of all signals at that level, thus controlling the propagation delay of the clock interconnects.
Current techniques are limited by the number of clock cycles needed to achieve skew correction and significant area and power overhead. Key component of our design is an active deskew buffer using a Transmission-Gate. This provides online clock skew correction within one clock cycle of the skew occurrence. The design has been validated using Monte-Carlo simulations in 180nm, 90nm, 65nm and 45nm technologies. Simulation results show up to 50% reduction in the clock skew for 180nm technology, as compared to other techniques. Also, significant improvement in speed is achieved, 11% reduction in total power consumed (under worst case skew), and an average of 6% power reduction for the loaded deskew system. The approach can be applied to clock networks in large System on Chip (SoC) designs.
