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Abstract
The four arithmetic operations that are performed in microprocessors are addition, subtraction, multiplication and division. Studies show that division is not carried out as fast as the other operations. The method of division and multiplication are very similar, as both have series of additions, subtractions and shifts. In multiplication, the multiplier is shifted left and added to the multiplicand and we shift the multiplier again for the next cycle and so on. Similarly, in division, the divisor is shifted to left and subtracted from the dividend and estimate the quotient. But division is complicated than multiplication where we have to estimate what multiple of the divisor leads to the dividend. Floating point division is the topic of the thesis.
It is widely used in various fields such as Multimedia, Cryptology, Signal processing etc. Various algorithms have been proposed in the past years for floating point division, which show different quotient selection logics. The design of the quotient selection logic is an important factor for improving the speed.
Based on the algorithm proposed by Burgess N, quotient selection logic is proposed in this thesis. This logic of quotient digit selection is independent of the divisor and is a function of two most significant bits of the dividend or the partial remainder.
If the division is represented in the following way,[special characters omitted]
By making x so small that the denominator is nearly equal to 1, we can approximate the numerator to be the quotient.
The floating point numbers in the range [1,2) are considered here and the requirements are
The dividend and the divisor are pre-scaled such that x < 1/r where r = 2. Division is performed in iterations based on the two bits of the partial remainder.
The division is performed in iterative steps and is a restoring division. The range of numbers [1.5, 2) need to be pre-scaled in order to satisfy the condition.
