A High-Performance Quadruple-Node-Upset-Tolerant Latch Design and an Algorithm for Tolerance Verification of Hardened Latches

Abstract

With the development of semiconductor technology, the shrinking of feature size in integrated circuits has made them more sensitive to multiple-node-upsets (MNUs). Researchers have proposed various circuit-hardened methods, such as hardened latches, to address this issue. Currently, the reliability verification of latches relies on complex EDA tools, such as HSPICE, Cadence Virtuoso, and other tools for error injection. Therefore, this article proposes a high-performance quadruple-node-upset (QNU) tolerant latch design, called the HQNUT latch, based on 32 nm CMOS technology. Additionally, an algorithm-based latch verification process is proposed to enhance the efficiency and reliability of latch verification. This approach enables a fast and accurate assessment of the latch’s fault-tolerant capability. Due to clock gating technology and high-speed path technology, HQNUT’s power consumption and delay are reduced. Simulation results show that the proposed algorithm can certify the soft-error-tolerability of hardened Latches. Compared with existing QNU-tolerable hardened latches, the proposed latch reduced power consumption, area, delay, and power-delay product (PDP) by about 36.9%, 5.6%, 19.8%, and 46.4%, respectively.