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In electronics manufacturing, a Surface Mount Technology (SMT) line includes discrete machines (such as printer, pick-and-place, and soldering equipment) and batch processing machines (such as Environmental Stress Screening (ESS) chambers, systems test chambers, and burn-in test chambers). The discrete machines are typically dedicated to a customer or a product type. However, the batch processing machines are used to process the jobs from various lines. Improving the utilization of the discrete machines has been a subject of interest for several decades. However, the performance improvements for batch processing machines—especially in a flow shop—are not well researched. These machines are typically expensive and a bottleneck. Consequently, the utilization of these machines must be improved to increase the throughput.
There are two important and dependent decisions to be made for a batch processing machine. They are (1) batching—how to form batches and (2) scheduling—how to sequence the batches. Scheduling batch processing machines to minimize the makespan, Cmax, is typically NP-hard and the literature is replete with heuristics. It is common to have two batch processing machines in a flow shop. Since scheduling a batch processing machine to minimize Cmax is itself NP-hard, most of the research work is limited to scheduling single or identical parallel batch processing machines. Consequently, this research effort will propose and investigate the application of various solution approaches to minimize Cmax of two batch processing machines in a flow shop.
The primary objectives of this research are (1) to identify the underlying properties of the problem under study, (2) to develop a heuristic, SA and a GA for the problem under study and, (3) to compare the solution quality and run time of these approaches against each other and with a commercial solver using randomly generated problem instances. (Abstract shortened by UMI.)