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Introduction
Nowadays, large numbers of applications benefit from functional units like squaring and cubic operations. These operations have frequent use in digital signal processing (DSP) applications such as image compression, decoding, demodulator, adaptive filters, least mean squaring and so on. The application of square and cube is also found in cryptography, graphic processor and rectangular to polar conversions in various circuits wherever complete precision result is not needed. Thus, continuous efforts are being made to improvise the design parameters of any computational blocks, and this leads to the improvement of the overall performance in terms of speed, area and consumed power [1]. Most frequently, squaring and cubic units are implemented using existing multiplier techniques [1, 2]; however, multiplication operation leads to repetitive addition operations. Again binary addition is considered to be most time-consuming operation in DSP processor. The overall area and performance of different applications can be improved using dedicated squaring and cubing algorithms of Vedic mathematics.
Vedic mathematics is the most proficient alternative to conventional mathematics as it simplifies and converts larger computation to smaller one. The whole Vedic mathematics is based on 16 sutra (or algorithms) providing unique and simple techniques to various mathematical computations. The Vedic algorithms are equally suited for binary platforms providing improvement to various designs parameters for computing arithmetic operations, as reported in [2–7]. The book (Maharaja, 2009; Tirthaji, 1965; Vedic mathematics, 2007) elaborates the Vedic mathematics focusing on all 16 significant sutras. The ‘Yavadunam’ sutra is one of the sutra from the 16 sutras of Vedic mathematics [8].
Discussing about various state-of-art square, cube architecture, Ercegovac et al. [9] have proposed different computational units such as reciprocal, square root, inverse square root, multiplication and cube based on argument reduction and series expansion. Authors have computed the cube operation using two k-bit multiplication, where k is between one quarter and one third of length of the operand size. In [10, 11], Liddicoat et al. have proposed a parallel cubic unit. Authors have discussed the application of proposed work with Newton–Raphson and Taylor series function. The performance and area requirement of cubing unit up-to 54-bit operands is also studied and claim their cubing unit is 25–30% faster than cube using multiplier. In [12], a cube architecture based on...