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Introduction
Network-on-chip (NoC) is a communication infrastructure used to interconnect various IP modules in a system-on-chip (SoC). NoC is composed of links, routers and network adapters (NAs) as shown in Fig. 1. Links physically connect the nodes and implement the communication. The router implements the communication protocol and the NA or network interface (NI) [1] makes the logical connection between the IP cores and the network. Communication in NoC is based on modules connected via a network of routers. Communication starts with the source processing node and ends with the destination processing node through interconnect. The significance of maintaining interconnect ability is required to achieve system performance.
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To provide reliable data communication, reliable channels with integrated ECC are proposed for on-chip interconnection networks as shown in Fig. 1. Deep sub micron (DSM) technology involves the integration of billions of transistors on a single die. In infrastructure such as an SoC, bus-based communication is not sufficient to handle power, area, and speed trade-off. NoC is the conventional solution to on-chip communication-related issues. The implementation of the NoC design model is facing design issues related to efficient interconnect fabric with technology limitations. Research analysis should address device-level defects that are present in technologies used in systems, to deliver high levels of reliability [2]. It should also look to satisfy constraints like low energy consumption [3]. In nanoscale technology, there is an increased interconnect density. Due to the supply voltage scaling, at higher clock rates on-chip interconnect wires suffer increased power consumption, and have reduced reliability because of the crosstalk. To cope with these problems, these encoding and decoding strategies are needed, but they cause delay. So any new encoding and decoding strategies should also ensure that the processing latency in the channel is reduced. This will help to facilitate high-frequency performance. The capacitive coupling causes delay problem. The gate delay has been reduced and the global interconnection wire delay has been increased due to scaling in DSM [2, 4–6]. To reduce the delay, the crosstalk avoidance codes are proposed in [7, 8]. The power consumption is increased because of high parasitic capacitance and coupling capacitance [9, 10]. To reduce the power consumption of interconnection link wires of NoC, low power coding techniques such...